# US 11,442,807 B2 · Error correction code (ECC) operations in memory

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- Number: US 11,442,807 B2
- Document ID: US11442807B2
- Status: Granted
- Kind: B2
- Application number: 17/157,001
- Filed: 2021-01-25
- Published: 2021-05-13
- Granted: 2022-09-13
- Earliest claimed: 2016-04-05
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Gerard A. Kreifels
- Web page: https://patentgrep.com/patent/US11442807B2

## CPC

- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- H03M 13/2942: {wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits}
- H03M 13/618: {Shortening and extension of codes}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.

## Claims

### Claim 1

A system, comprising:
a memory; and
a controller coupled to the memory and configured to read on a codeword from the memory, wherein the codeword includes:
user data; and
a first number of error correction code (ECC) bits that are generated based on an encoding matrix with columns having a first odd weight and a second odd weight to reduce a gap between weights of the columns and maintain a difference between weights of any two adjacent columns of the encoding matrix, wherein an odd weight includes an odd number of bits having a binary value of 1;
compare the first number of ECC bits to a second number of ECC bits that are generated at least partially based on the codeword read from the memory;
correct a single error in the codeword in response to a result of the comparison having an odd weight; and
detect that there are two errors in the codeword in response to a result of the comparison having an even weight.

### Claim 2 (depends on 1)

The system of claim 1, wherein every other column starting with a first column of the encoding matrix has the first odd weight and every other column starting with a second column has the second odd weight that is different than the first odd weight.

### Claim 3 (depends on 1)

The system of claim 1, wherein the first odd weight and the second odd weight are consecutive odd integers such that a difference between the first odd weight and the second odd weight is 2.

### Claim 4 (depends on 1)

The system of claim 1, wherein:
the encoding matrix comprises a number of data patterns; and
the controller is configured to identify, in response to the result of the comparison having an odd weight, a bit position of an erroneous bit based on the comparison between the result to the number of data patterns.

### Claim 5 (depends on 1)

The system of claim 1, wherein the controller is configured to identify, in response to the result of the comparison having an even weight, that there are two errors in the codeword, while a respective bit position of erroneous bits is unidentifiable.

### Claim 6 (depends on 1)

The system of claim 1, wherein the encoding matrix comprises a number of data patterns, wherein each one of the number of data patterns is assigned to each bit position of the codeword.

### Claim 7 (depends on 1)

The system of claim 1, wherein the controller is configured to perform, to compare the first number of ECC bits to the second number of ECC bits, an XOR operation on the first number of ECC bits and the second number of ECC bits.

### Claim 8

A system, comprising:
a memory; and
a controller coupled to the memory and configured to:
generate a first number of error correction code (ECC) bits from user data using an encoding matrix comprising a number of data patterns, wherein:
columns of the encoding matrix comprise a first odd weight and a second odd weight to reduce a gap between weights of the columns and maintain a difference between weights of any two adjacent columns of the encoding matrix; and
an odd weight includes an odd number of bits having a binary value of 1 and an even weight includes an even number of bits having a binary value of 1;
write the user data and the first number of ECC bits to the memory;
compare, in response to reading the user data and the first ECC data from the memory, the first number of ECC bits to a second number of ECC bits, wherein the second number of ECC bits are generated from decoding the user data and the first number of ECC bits read from the memory using a decoding matrix comprising at least the number of data patterns;
in response to a result of the comparison having an odd weight that indicates a single error in the user data and the first number of ECC bits, correct the single error; and
in response to a result of the comparison having an even weight, detect that there are two errors in the user data and the first number of ECC bits.

### Claim 9 (depends on 8)

The system of claim 8, wherein the columns of the encoding matrix has no other weights other than the first weight and the second weight.

### Claim 10 (depends on 8)

The system of claim 8, wherein columns of the decoding matrix has a first even weight and a second even weight.

### Claim 11 (depends on 10)

The system of claim 10, wherein the first even weight is a consecutive integer of the first odd weight and the second even weight is a consecutive integer of the second odd weight.

### Claim 12 (depends on 10)

The system of claim 10, wherein the first even weight and the second even weight are consecutive even integers such that a difference between the first even weight and the second even weight is 2.

### Claim 13 (depends on 8)

The system of claim 8, wherein:
the number of data patterns is a first number of data patterns, wherein each one of the first number of data patterns is assigned to a respective bit position of the user data; and
the decoding matrix further comprises a second number of data patterns, wherein each one of the second number of data patterns is assigned to a respective bit position of the first number of ECC bits.

### Claim 14 (depends on 13)

The system of claim 13, wherein the controller is configured to identify, in response to the result of the comparison having an odd weight, a bit position of an erroneous bit within the user data or the first number of ECC bits based on the comparison of the result of the comparison to the first number of ECC bits or to the second number of ECC bits.

### Claim 15 (depends on 13)

The system of claim 13, wherein a quantity of bits of the second number of data patterns is equal to a quantity of bits of the first number of ECC bits.

### Claim 16 (depends on 8)

The system of claim 8, wherein the controller is configured to determine there is no error in the codeword in response to a result of the comparison having a zero weight.

### Claim 17 (depends on 8)

The system of claim 8, wherein the first weight and the second weight are consecutive odd integers.

### Claim 18

A method, comprising:
generating a first number of error correction code (ECC) bits based on user data and an encoding matrix, wherein:
columns of the encoding matrix comprise a first odd weight and a second odd weight to reduce a gap between weights of the columns and maintain a difference between weights of any two adjacent columns of the encoding matrix; and
an odd weight includes an odd number of bits having a binary value of 1 and an even weight includes an even number of bits having a binary value of 1;
writing a codeword including the user data and the first number of ECC bits to the memory;
generating a second number of ECC bits based at least in part on the user data and the first number of ECC bits read from the memory to compare the first number of ECC bits to the second number of ECC bits;
correcting a single error in the codeword in response to a syndrome corresponding to a result of the comparison having an odd weight; and
detecting that there are two errors in the codeword in response to a syndrome corresponding to a result of the comparison having an even weight.

### Claim 19 (depends on 18)

The method of claim 18, wherein generating the first number of ECC bits based on user data and an encoding matrix further comprises performing a number of XOR operations on the user data and the encoding matrix, wherein a quantity of the number of XOR operations performed is proportional to a quantity of bits having a binary value of 1 of the user data.

### Claim 20 (depends on 18)

The method of claim 18, wherein the method further comprises performing, to compare the first number of ECC bits to the second number of ECC bits, a number of XOR operation on the first number of ECC bits and a second number of ECC bits.