# US 11,442,800 B2 · Watchdog circuit systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,800 B2 - Document ID: US11442800B2 - Status: Granted - Kind: B2 - Application number: 16/985,362 - Filed: 2020-08-05 - Published: 2021-09-23 - Granted: 2022-09-13 - Earliest claimed: 2020-03-17 - Assignees: Hamilton Sundstrand Corporation - Applicants: Hamilton Sundstrand Corporation - Inventors: Rajeeva Gopala Krishna; Shihab T. A. Muhammed - Web page: https://patentgrep.com/patent/US11442800B2 ## CPC - G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs} - G06F 9/4403: {Processor initialisation} - H03K 3/037: Bistable circuits - H03K 5/00: Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) - H03K 5/19: Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) - H03K 21/08: Output circuits - H03K 2005/00078: {Fixed delay} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A windowed watchdog circuit system can include a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold. The windowed watchdog circuit system can include a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorted than the fast threshold. The windowed watchdog circuit system can be configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively. ## Claims ### Claim 1 A windowed watchdog circuit system, comprising: a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold time; a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorter than the fast threshold time, wherein the windowed watchdog circuit system is configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively. ### Claim 2 (depends on 1) The system of claim 1, wherein the fast timer system includes a fast timer module configured to output a first module state, and to output a second module state for the fast threshold time after receiving a watchdog strobe signal from the processor. ### Claim 3 (depends on 2) The system of claim 2, wherein the fast timer system includes a latch having a state input, a clock input, and a latch output, wherein the state input of the latch is operatively connected to the fast timer module to receive the second module state. ### Claim 4 (depends on 3) The system of claim 3, wherein the clock input is configured to be connected to the processor to receive the watchdog strobe signals. ### Claim 5 (depends on 4) The system of claim 4, wherein the latch is configured to switch from a first output state indicating the gap time is equal to or longer than the fast time threshold to a second output state indicating the gap time is shorter than the fast time threshold when the state input is receiving the second module state and the clock input receives a watchdog strobe signal. ### Claim 6 (depends on 5) The system of claim 5, wherein the fast timer system includes a delay module configured to add a predetermined time delay to the first module state and/or the second module state from the fast timer module such that the state input of the latch receives the first module state and/or the second module state from the fast timer module delayed from the watchdog strobe signal received by the clock input. ### Claim 7 (depends on 6) The system of claim 6, wherein the latch is a D-type latch. ### Claim 8 (depends on 6) The system of claim 6, further comprising a logic block connected to the latch output and the slow timer module and configured to output a normal state when both the slow timer module and the fast timer system are not outputting the slow threshold state and the fast threshold state, respectively, and wherein the logic block is configured to output a reset state when either the slow threshold state or the fast threshold state is received by the logic block. ### Claim 9 (depends on 8) The system of claim 8, wherein the logic block is an AND block. ### Claim 10 (depends on 9) The system of claim 9, further comprising an OR block configured to output the reset state if the AND block outputs the reset state and if a watchdog mask does not output a mask state. ### Claim 11 (depends on 1) The system of claim 1, further comprising the processor. ### Claim 12 A vehicle electronics device, comprising: a windowed watchdog circuit system, comprising: a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold time; a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorter than the fast threshold time, wherein the windowed watchdog circuit system is configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively. ### Claim 13 (depends on 12) The device of claim 12, wherein the fast timer system includes a fast timer module configured to output a first module state and to output a second module state for the fast threshold time after receiving a watchdog strobe signal from the processor. ### Claim 14 (depends on 13) The device of claim 13, wherein the fast timer system includes a latch having a state input, a clock input, and a latch output, wherein the state input of the latch is operatively connected to the fast timer module to receive the second module state. ### Claim 15 (depends on 14) The device of claim 14, wherein the clock input is configured to be connected to the processor to receive the watchdog strobe signals. ### Claim 16 (depends on 15) The device of claim 15, wherein the latch is configured to switch from a first output state indicating the gap time is equal to or longer than the fast time threshold to a second output state indicating the gap time is shorter than the fast time threshold when the state input is receiving the second module state and the clock input receives a watchdog strobe signal. ### Claim 17 (depends on 16) The device of claim 16, wherein the fast timer system includes a delay module configured to add a predetermined time delay to the first module state and/or the second module state from the fast timer module such that the state input of the latch receives the first module state and/or the second module state from the fast timer module delayed from the watchdog strobe signal received by the clock input. ### Claim 18 (depends on 17) The device of claim 17, wherein the latch is a D-type latch. ### Claim 19 (depends on 18) The device of claim 18, further comprising a logic block connected to the latch output and the slow timer module and configured to output a normal state when both the slow timer module and the fast timer system are not outputting the slow threshold state and the fast threshold state, respectively, and wherein the logic block is configured to output a reset state when either the slow threshold state or the fast threshold state is received by the logic block. ### Claim 20 A fast timer system for a circuit, comprising: a fast timer module configured to output a first module state and to output a second module state for a fast threshold time after receiving a watchdog strobe signal from the processor; a latch having a state input, a clock input, and a latch output, wherein the state input of the latch is operatively connected to the fast timer module to receive the second module state, wherein the clock input is configured to be connected to the processor to receive the watchdog strobe signals, wherein the latch is configured to switch from a first output state indicating that watchdog strobe signal gap time is equal to or longer than the fast time threshold to a second output state indicating the gap time is shorter than the fast time threshold when the state input is receiving the second module state and the clock input receives a watchdog strobe signal; and a delay module configured to add a predetermined time delay to the first module state and/or the second module state from the fast timer module such that the state input of the latch receives the first and/or second module state from the fast timer module delayed from the watchdog strobe signal received by the clock input.