Hardware accelerator method, system and device

A system, comprising:

• an addressable memory array;
• one or more processing cores;
• and
• an accelerator framework coupled to the addressable memory and including a Multiply ACcumulate (MAC) hardware accelerator cluster, the MAC hardware accelerator cluster having:
• a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system, wherein converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer;
• a plurality of MAC hardware accelerators, which, in operation, perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations;
• and
• a residual-to-binary converter, wherein a MAC hardware accelerator of the plurality of MAC hardware accelerators comprises a (m −1)-bit multiplier and a plurality of logic gates.

A Multiply ACcumulate (MAC) hardware accelerator, comprising:

• a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system, wherein converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer;
• a MAC circuit, which, in operation, performs modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations;
• and
• a residual-to-binary converter, wherein the MAC circuit includes a seven-bit multiply-and-accumulate circuit, a six-bit multiply-and-accumulate circuit, and a three-bit multiply-and-accumulate circuit.

A Multiply ACcumulate (MAC) hardware accelerator, comprising:

• a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system, wherein converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer;
• a MAC circuit, which, in operation, performs modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations;
• and
• a residual-to-binary converter, wherein the MAC circuit comprises a (m −1)-bit multiplier and a plurality of logic gates.

A method, comprising:

• converting, using a binary-to-residual converter, a binary input to a residual number system, the converting including a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer;
• multiplying, using a Multiple ACcumulate (MAC) circuit, the converted binary input by a second input, the multiplying including a modulo 2m multiply-and-accumulate operation and a modulo 2m−1 multiply-and-accumulate operation;
• and
• generating, using a residual-to-binary converter, a binary output based on a result of the multiplying, wherein the MAC circuit comprises a (m −1)-bit multiplier and a plurality of logic gates.