# US 11,442,666 B2 · Storage system and dual-write programming method with reverse order for secondary block > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,666 B2 - Document ID: US11442666B2 - Status: Granted - Kind: B2 - Application number: 17/182,485 - Filed: 2021-02-23 - Published: 2022-05-19 - Granted: 2022-09-13 - Earliest claimed: 2020-11-17 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Yogendra Singh Sikarwar; Ankit Naghate; Milind Giradkar; Rakshit Tikoo - Web page: https://patentgrep.com/patent/US11442666B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/064: {Management of blocks} - G06F 3/0673: {Single storage device} - G06F 11/1666: {where the redundant component is memory or memory area} - G11C 11/1657: {Word-line or row circuits} - G11C 11/1675: {Writing or programming circuits or methods} - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 29/74: {using duplex memories, i.e. using dual copies} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant - G11C 2213/71: Three dimensional array - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A storage system has a memory with primary and secondary blocks. Data is stored redundantly in the primary and secondary memory blocks but in a different programming order. For example, data is programmed in the first memory block starting at a first wordline and ending at a last wordline, while data is programmed in the second memory block starting at the last wordline and ending at the first wordline. ## Claims ### Claim 1 A storage system comprising: a memory comprising a multi-level cell (MLC) block of memory, a primary single-level cell (SLC) block of memory, and a secondary SLC block of memory, wherein the primary and secondary SLC blocks of memory comprise a plurality of wordlines; and a controller configured to: program a plurality of data segments in the plurality of wordlines in the primary SLC block of memory in a first programming order without skipping any wordlines in the prima SLC block, wherein all of the wordlines in the primary SLC block are programmed; program a redundant version of the plurality of the data segments in the plurality of wordlines in the secondary SLC block of memory in a second programming order that is opposite the first programming order without skipping any wordlines in the secondary SLC block, wherein all of the wordlines in the secondary SLC block are programmed, and wherein a given data segment and its redundant version are stored in different wordline numbers in the primary and secondary SLC blocks; and fold the plurality of data segments into the MLC block of memory, wherein a data segment that is readable from the primary SLC block is read from the primary SLC block, and wherein a data segment that is unreadable from the primary SLC block is read from the secondary SLC block. ### Claim 2 (depends on 1) The storage system of claim 1, wherein the first programming order consecutively programs wordlines starting at a first wordline and ending at a last wordline, and wherein the second programming order consecutively programs wordlines starting at the last wordline and ending at the first wordline, or vice versa. ### Claim 3 (depends on 1) The storage system of claim 1, wherein the controller is further configured to determine whether the data comprises a boot block, and wherein the primary and secondary SLC blocks are programmed with the data in response to determining that the data comprises a boot block. ### Claim 4 (depends on 1) The storage system of claim 1, wherein the controller is further configured to determine whether the data comprises control data, and wherein the primary and secondary SLC blocks are programmed with the data in response to determining that the data comprises control data. ### Claim 5 (depends on 1) The storage system of claim 1, wherein the memory comprises a three-dimensional memory. ### Claim 6 In a storage system comprising a memory comprising a multi-level cell (MLC) block of memory, a primary single-level cell (SLC) block of memory, and a secondary SLC block of memory, wherein the primary and secondary SLC blocks of memory comprise a plurality of wordlines, a method comprising: receiving a plurality of data segments to be stored in the memory; performing a dual-write programming operation by: storing the plurality of data segments in the primary SLC block of memory starting at a first wordline and ending at a last wordline, without skipping any wordlines in the primary SLC block, wherein all of the wordlines in the primary SLC block are programmed; and storing a redundant version of the plurality of data segments in the plurality of wordlines in the secondary SLC block of memory starting at the last wordline and ending at the first wordline without skipping any wordlines in the secondary SLC block, wherein all of the wordlines in the secondary SLC block are programmed, and wherein a given data segment and its redundant version are stored in different wordline numbers in the primary and secondary SLC blocks; and folding the plurality of data segments into the MLC block of memory, wherein a data segment that is readable from the primary SLC block is read from the primary SLC block, and wherein a data segment that is unreadable from the primary SLC block is read from the secondary SLC block. ### Claim 7 (depends on 6) The method of claim 6, wherein the primary and secondary SLC blocks of memory comprise single-level cells. ### Claim 8 (depends on 6) The method of claim 6, further comprising determining whether the data comprises a boot block, and wherein the dual-write programming operation is performed in response to determining that the data comprises a boot block. ### Claim 9 (depends on 6) The method of claim 6, further comprising determining whether the data comprises control data, and wherein the dual-write programming operation is performed in response to determining that the data comprises control data. ### Claim 10 (depends on 6) The method of claim 6, wherein the memory comprises a three-dimensional memory. ### Claim 11 A storage system comprising: a memory comprising a multi-level cell (MLC) block of memory, a primary single-level cell (SLC) block of memory, and a secondary SLC block of memory, wherein the primary and secondary SLC blocks of memory comprise a plurality of wordlines; means for programming a plurality of data segments in the plurality of wordlines in the primary SLC block of memory in a first programming order without skipping any wordlines in the primary SLC block, wherein all of the wordlines in the primary SLC block are programmed; means for programming a redundant version of the plurality of the data segments in the plurality of wordlines in the secondary SLC block of memory in a second programming order that is opposite the first programming order, without skipping any wordlines in the secondary SLC block, wherein all of the wordlines in the secondary SLC block are programmed, and wherein a given data segment and its redundant version are stored in different wordline numbers in the primary and secondary SLC blocks; and means for folding the plurality of data segments into the MLC block of memory, wherein a data segment that is readable from the primary SLC block is read from the primary SLC block, and wherein a data segment that is unreadable from the primary SLC block is read from the secondary SLC block. ### Claim 12 (depends on 11) The storage system of claim 11, wherein data is programmed in the primary SLC block of memory starting at a first wordline and ending at a last wordline, and wherein data is programmed in the secondary SLC block of memory starting at the last wordline and ending at the first wordline. ### Claim 13 (depends on 11) The storage system of claim 11, further comprising means for determining whether the data should be redundantly programmed. ### Claim 14 (depends on 11) The storage system of claim 11, further comprising means for determining whether the data comprises a boot block, and wherein the primary and secondary SLC blocks are programmed with the data in response to determining that the data comprises a boot block. ### Claim 15 (depends on 11) The storage system of claim 11, further comprising means for determining whether the data comprises control data, and wherein the primary and secondary SLC blocks are programmed with the data in response to determining that the data comprises control data. ### Claim 16 (depends on 11) The storage system of claim 11, wherein the memory comprises a three-dimensional memory.