# US 11,442,664 B2 · Memory system and method of operating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,442,664 B2
- Document ID: US11442664B2
- Status: Granted
- Kind: B2
- Application number: 17/069,938
- Filed: 2020-10-14
- Published: 2021-01-28
- Granted: 2022-09-13
- Earliest claimed: 2017-07-18
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Kwang Su Kim
- Web page: https://patentgrep.com/patent/US11442664B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0611: {in relation to response time}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00)
- G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 )
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/12: Programming voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 2207/2272: Latency related aspects
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.

## Claims

### Claim 1

A method for a memory controller controlling a non-volatile memory device, the method comprising:
receiving a plurality of commands from a host;
queueing a command among the plurality of commands into a queue status register based on a priority of the plurality of commands; and
executing a next command among the plurality of commands to be performed after the command based on the priority of the plurality of commands and a category of the plurality of commands,
wherein the queueing comprises:
setting a status of the command as a set status; and
setting the status of the command as a clear status after the memory device starts to perform an operation corresponding to the command.

### Claim 2 (depends on 1)

The method of claim 1, wherein the executing the next command comprises setting a status of the next command as the set status.

### Claim 3 (depends on 2)

The method of claim 2, wherein the plurality of commands include a write command and a read command.

### Claim 4 (depends on 3)

The method of claim 3, wherein the executing the next command comprises setting a status of the read command to the set status prior to the write command for a predetermined time.

### Claim 5 (depends on 1)

The method of claim 1, wherein the priority of the plurality of commands is an order provided from the host.

### Claim 6

An apparatus, comprising:
a memory device; and
a controller coupled to the memory device and configured to:
receive a plurality of commands from a host;
queue a command among the plurality of commands into a queue status register based on a priority of the plurality of commands;
set a status of the command as a set status;
set the status of the command as a clear status after the memory device starts to perform an operation corresponding to the command; and
execute a next command among the plurality of commands to be performed after the command based on the priority of the plurality of commands and a category of the plurality of commands.