# US 11,442,638 B2 · Status management in storage backed memory package

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- Number: US 11,442,638 B2
- Document ID: US11442638B2
- Status: Granted
- Kind: B2
- Application number: 17/036,866
- Filed: 2020-09-29
- Published: 2021-01-28
- Granted: 2022-09-13
- Earliest claimed: 2018-02-08
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Michael Burns; Gary R. Van Sickle; Jeffery J. Leyda
- Web page: https://patentgrep.com/patent/US11442638B2

## CPC

- G06F 3/0634: {by changing the state or mode of one or more devices}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0637: {Permissions}
- G06F 3/068: {Hybrid storage device}
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Devices and techniques for status management in storage backed memory are disclosed herein. An encoded message can be received at a first interface of the memory package. Here, the memory package also includes a second interface to a host. The message can be decoded to obtain a decoded message that includes an attribute. The attribute can be compared a set of attributes that correspond to an advertised status of the memory package. The comparison enables a determination that the attribute is in the set of attributes. The advertised status of the memory package can then be modified in response to the determination that the attribute is in the set of attributes.

## Claims

### Claim 1

A memory system comprising:
a memory controller;
an interface for communication between the memory controller and a host; and
a decoder coupled to the interface, the decoder configured to perform operations comprising:
decoding an encoded message from the host to obtain a decoded message, the decoded message comprising a request to write to a command register of the memory controller, and the decoded message further comprising a message attribute;
prior to providing the decoded message to the memory controller for executing the request to write to the command register:
inspecting the decoded message to determine whether the request to write to the command register is associated with an operation that corresponds to an advertised status of the memory system, the inspecting of the decoded message comprising determining whether the message attribute is in a set of attributes that corresponds to the advertised status, and the advertised status being accessible by the host via the interface; and
modifying the advertised status of the memory system in response to determining that the message attribute is in the set of attributes; and
providing the decoded message to the memory controller for executing the request.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the interface comprises an Inter-Integrated Circuit (I2C) bus.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the memory system is part of a non-volatile dual in-line memory module (NVDIMM).

### Claim 4 (depends on 1)

The memory system of claim 1, wherein the advertised status indicates whether the operation in progress for the memory controller.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the set of attributes are defined by a Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backed Interface (BAEBI) family of standards.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein the message attribute is an address.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the address is a page designator.

### Claim 8

A method comprising:
decoding, at a memory system, an encoded message from a host to obtain a decoded message, the decoded message comprising a request to write to a command register of a memory controller of the memory system, the decoded message further comprising a message attribute;
prior to providing the decoded message to the memory controller for executing the request to write to the command register:
inspecting the decoded message to determine whether the request to write to the command register is associated with an operation that corresponds to an advertised status of the memory system, the inspecting the decoded message comprising determining whether the message attribute is in a set of attributes that corresponds to the advertised status, and the advertised status being accessible by the host; and
modifying the advertised status of the memory system in response to determining that the message attribute is in the set of attributes; and
providing the decoded message to the memory controller for executing the request.

### Claim 9 (depends on 8)

The method of claim 8, wherein the advertised status is accessible by the host via an interface of the memory system, the interface comprising an Inter-Integrated Circuit (I2C) bus.

### Claim 10 (depends on 8)

The method of claim 8, wherein the memory system is part of a non-volatile dual in-line memory module (NVDIMM).

### Claim 11 (depends on 8)

The method of claim 8, wherein the advertised status indicates whether the operation in progress for the memory controller.

### Claim 12 (depends on 8)

The method of claim 8, wherein the set of attributes are defined by a Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backed Interface (BAEBI) family of standards.

### Claim 13 (depends on 8)

The method of claim 8, wherein the message attribute is an address.

### Claim 14 (depends on 13)

The method of claim 13, wherein the address is a page designator.

### Claim 15

At least one non-transitory machine readable medium including instructions, when executed by processing circuitry of a memory system, cause the memory system to perform operations comprising:
decoding an encoded message from a host to obtain a decoded message, the decoded message comprising a request to write to a command register of a memory controller of the memory system, the decoded message further comprising a message attribute;
prior to providing the decoded message to the memory controller for executing the request to write to the command register:
inspecting the decoded message to determine whether the request to write to the command register is associated with an operation that corresponds to an advertised status of the memory system, the inspecting the decoded message comprising determining whether the message attribute is in a set of attributes that corresponds to the advertised status, and the advertised status being accessible by the host; and
modifying the advertised status of the memory system in response to determining that the message attribute is in the set of attributes; and
providing the decoded message to the memory controller for executing the request.

### Claim 16 (depends on 15)

The at least one non-transitory machine readable medium of claim 15, wherein the advertised status is accessible by the host via an interface of the memory system, the interface comprising an Inter-Integrated Circuit (I2C) bus.

### Claim 17 (depends on 15)

The at least one non-transitory machine readable medium of claim 15, wherein the memory system is part of a non-volatile dual in-line memory module (NVDIMM).

### Claim 18 (depends on 15)

The at least one non-transitory machine readable medium of claim 15, wherein the advertised status indicates whether the operation in progress for the memory controller.

### Claim 19 (depends on 15)

The at least one non-transitory machine readable medium of claim 15, wherein the message attribute is an address.

### Claim 20 (depends on 19)

The at least one non-transitory machine readable medium of claim 19, wherein the address is a page designator.