# US 11,442,517 B2 · On-chip passive power supply compensation circuit and operation unit, chip, hash board and computing device using same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,517 B2 - Document ID: US11442517B2 - Status: Granted - Kind: B2 - Application number: 17/251,659 - Filed: 2019-06-06 - Published: 2021-08-26 - Granted: 2022-09-13 - Earliest claimed: 2018-09-20 - Assignees: Canaan Creative Co., Ltd. - Applicants: Canaan Creative Co., Ltd. - Inventors: Jieyao Liu; Nangeng Zhang; Jingjie Wu; Shenghou Ma - Web page: https://patentgrep.com/patent/US11442517B2 ## CPC - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains. ## Claims ### Claim 1 An on-chip passive power supply compensation circuit, comprising: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground; wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains; wherein a first power supply end and a first ground end are formed at both ends of each of the isolation regions, and the first power supply end and/or the first ground end are configured for supplying a reference voltage to the power supply compensation units; a second power supply end and a second ground end are formed at both ends of each of the to-be-powered voltage domains, and the power supply compensation units provide power supply compensation to the second power supply end and/or the second ground end. ### Claim 2 (depends on 1) The on-chip passive power supply compensation circuit according to claim 1, wherein the power supply compensation units provide power supply compensation to the to-be-powered voltage domains by working in a saturation state. ### Claim 3 (depends on 2) The on-chip passive power supply compensation circuit according to claim 2, wherein taking the reference voltage for reference, when a voltage variation range of the second power supply end and/or the second ground end exceeds a threshold value of the power supply compensation units, the power supply compensation units work in the saturation state. ### Claim 4 (depends on 3) The on-chip passive power supply compensation circuit according to claim 3, wherein the power supply compensation units are switching transistors. ### Claim 5 (depends on 4) The on-chip passive power supply compensation circuit according to claim 4, wherein the switching transistors are PMOS switching transistors and/or NMOS switching transistors. ### Claim 6 (depends on 5) The on-chip passive power supply compensation circuit according to claim 5, wherein the PMOS switching transistors and/or the NMOS switching transistors are one or plural. ### Claim 7 (depends on 6) The on-chip passive power supply compensation circuit according to claim 6, wherein one or more semiconductor devices are formed in the to-be-powered voltage domains, and the first power supply end and/or the first ground end supply a substrate bias voltage to the semiconductor devices. ### Claim 8 (depends on 7) The on-chip passive power supply compensation circuit according to claim 7, wherein the semiconductor devices comprise the PMOS transistors and/or the NMOS transistors, the first power supply end supplies the substrate bias voltage to the PMOS transistors, and the first ground end supplies the substrate bias voltage to the NMOS transistors. ### Claim 9 (depends on 1) The on-chip passive power supply compensation circuit according to claim 1, further comprising a voltage stabilizing unit connected in parallel to both ends of each of the isolation regions. ### Claim 10 (depends on 9) The on-chip passive power supply compensation circuit according to claim 9, wherein a first power supply end and a first ground end are formed at both ends of each of the isolation regions, and the first power supply end and/or the first ground end are configured for supplying a reference voltage to the power supply compensation units. ### Claim 11 (depends on 10) The on-chip passive power supply compensation circuit according to claim 10, wherein a second power supply end and a second ground end are formed at both ends of each of the to-be-powered voltage domains, and the power supply compensation units provide power supply compensation to the second power supply end and/or the second ground end. ### Claim 12 (depends on 11) The on-chip passive power supply compensation circuit according to claim 11, wherein the voltage stabilizing unit is configured for stabilizing a voltage of the first power supply end and/or the first ground end. ### Claim 13 (depends on 12) The on-chip passive power supply compensation circuit according to claim 12, wherein the voltage stabilizing unit comprises one or more of a resistor, a capacitor or a diode. ### Claim 14 (depends on 13) The on-chip passive power supply compensation circuit according to claim 13, wherein the voltage stabilizing unit is directly connected between the first power supply end and the first ground end, or connected between the first power supply end and the first ground end through an analog switch. ### Claim 15 (depends on 14) The on-chip passive power supply compensation circuit according to claim 14, wherein an analog switch is provided between the first ground end and the second ground end. ### Claim 16 (depends on 1) A data operation unit, comprising a control circuit, an operational circuit and a memory circuit interconnected, and one or more on-chip passive power supply compensation circuits, wherein the on-chip passive power supply compensation circuit is the on-chip passive power supply compensation circuit according to claim 1. ### Claim 17 (depends on 16) A chip, comprising at least one of the data operation units according to claim 16. ### Claim 18 (depends on 17) A hash board for a computing device, comprising at least one of the chips according to claim 17. ### Claim 19 (depends on 18) A computing device, comprising a power supply plate, a control board, a connection board, a radiator and a plurality of hash boards, the control board connected to the hash boards through the connection board, the radiator provided around the hash boards, and the power supply plate configured for supplying a power supply to the connection board, the control board, the radiator and the hash boards, wherein the hash board is the hash board according to claim 18.