# US 11,442,490 B1 · Low DCD clock signal generators

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- Number: US 11,442,490 B1
- Document ID: US11442490B1
- Status: Granted
- Kind: B1
- Application number: 17/383,820
- Filed: 2021-07-23
- Granted: 2022-09-13
- Earliest claimed: 2021-07-23
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Suvadip Banerjee
- Web page: https://patentgrep.com/patent/US11442490B1

## CPC

- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015})
- H03K 3/037: Bistable circuits
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

## Claims

### Claim 1

A clock signal generator comprising:
a clock source having first and second outputs;
a driver having a first input coupled to the first output of the clock source, a second input coupled to the second output of the clock source, a first output at which a first clock signal is output, and a second output at which a second clock signal is output;
a frequency divider having an input coupled to the second output of the clock source, a first output, and a second output;
a generator circuit having a first input coupled to the first output of the frequency divider, a second input coupled to the second output of the frequency divider, a first output at which a first chopper control signal is output, and a second output at which a second chopper control signal is output; and
a chopper circuit having a first input coupled to the first output of the driver, a second input coupled to the second output of the driver, a third input coupled to the first output of the generator circuit, a fourth input coupled to the second output of the generator circuit, a first output at which a first output signal is output and a second output at which a second output signal is output.

### Claim 2 (depends on 1)

The clock signal generator of claim 1, wherein the clock source includes:
an oscillator configured to generator an oscillator signal at an input frequency;
a buffer having an input configured to receive the oscillator signal and output a first intermediate clock signal at the first output of the clock source; and
an inverter having an input configured to receive the oscillator signal and output a second intermediate clock signal at the second output of the clock source.

### Claim 3 (depends on 1)

The clock signal generator of claim 1, wherein the driver includes:
a first buffer having the first input and the first output; and
a second buffer having the second input and the second output.

### Claim 4 (depends on 1)

The clock signal generator of claim 1, wherein the generator circuit includes:
a first NAND gate having the first input and the first output of the generator circuit; and
a second NAND gate having the second input and the second output of the generator circuit,
wherein the first NAND gate has a second input coupled to the second output of the generator circuit, and the second NAND gate has a second input coupled to the first output of the generator circuit.

### Claim 5 (depends on 4)

The clock signal generator of claim 4, wherein the generator circuit includes:
a first delay coupled between the first output of the generator circuit and the second input of the second NAND gate; and
a second delay coupled between the second output of the generator circuit and the second input of the first NAND gate.

### Claim 6 (depends on 1)

The clock signal generator of claim 1, wherein the chopper circuit includes:
a first pair of switches responsive to the first chopper control signal; and
a second pair of switches responsive to the second chopper control signal.

### Claim 7 (depends on 6)

The clock signal generator of claim 6, wherein the first pair of switches are configured to close in response to the first chopper signal to pass the first clock signal as the first output signal and to pass the second clock signal as the second output signal.

### Claim 8 (depends on 7)

The clock signal generator of claim 7, wherein the second pair of switches are configured to close in response to the second chopper signal to pass the first clock signal as the second output signal and to pass the second clock signal as the first output signal.

### Claim 9 (depends on 1)

The clock signal generator of claim 1, wherein the chopper circuit is configured to have a first state in which the first clock signal is passed as the first output signal and the second clock signal is passed as the second output signal, a second state in which the first clock signal is passed as the second output signal and the second clock signal is passed as the first output signal, and a third state in which a previous state is maintained.

### Claim 10 (depends on 2)

The clock signal generator of claim 2, wherein each of the first and second chopper control signals has a frequency that is half that of the input frequency.

### Claim 11

A clock signal generator comprising:
a complementary metal-oxide-semiconductor (CMOS) clock source including a CMOS oscillator having an output, a buffer having an input coupled to the output of the CMOS oscillator, and an inverter having an input coupled to the output of the CMOS oscillator;
a CMOS driver including a first delay and buffer assembly having an input coupled to an output of the buffer and a second delay and buffer assembly having an input coupled to an output of the inverter;
a D-type flip flop having a clock input coupled to the output of the inverter, a data input, a non-inverted output and an inverted output, the data input being coupled to the inverting output;
a non-overlapping generator circuit having a first input coupled to the non-inverting output of the D-type flip flop and a second input coupled to the inverting output of the D-type flip flop; and
a differential chopper circuit having a first input coupled to an output of the first delay and buffer assembly, a second input coupled to an output of the second delay and buffer assembly, a third input coupled to a first output of the non-overlapping generator circuit, and a fourth input coupled to a second output of the non-overlapping generator circuit.

### Claim 12 (depends on 11)

The clock signal generator of claim 11, wherein the differential chopper circuit is configured to have a first state in which a first clock signal output received at the first input of the differential chopper circuit is passed as a first output signal and a second clock signal received at the second input of the differential chopper is passed as the second output signal, a second state in which the first clock signal is passed as the second output signal and the second clock signal is passed as the first output signal, and a third state in which a previous state is maintained.

### Claim 13

A method comprising:
generating first and second intermediate clock signals, each at an input frequency;
applying the first and second intermediate clock signals to a driver to output first and second clock signals;
applying the second intermediate clock signal to a frequency divider to generate first and second divided signals;
applying the first and second divided signals to a generator circuit to generate first and second chopper control signals; and
applying the first and second clock signals and the first and second chopper control signals to a chopper circuit to generate first and second output signals based on the rising edges of the first clock signal.

### Claim 14 (depends on 13)

The method of claim 13, comprising:
passing the first clock signal as the first output signal and passing the second clock signal as the second output signal when the chopper circuit is in a first state;
passing the first clock signal as the second output signal and passing the second clock signal as the first output signal when the chopper circuit is in a third state; and
maintaining an immediate previous state when the chopper circuit is in a second state.

### Claim 15 (depends on 14)

The method of claim 14, comprising:
closing each of a first pair of switches of the chopper circuit to place the chopper circuit in the first state; and
closing each of a second pair of switches of the chopper circuit to place the chopper circuit in the second state.

### Claim 16 (depends on 13)

The method of claim 13, comprising:
applying the first divided signal to a first input of a first NAND gate of the generator circuit and applying a delayed second chopper signal to a second input of the first NAND gate to generate the first chopper signal.

### Claim 17 (depends on 13)

The method of claim 13, comprising:
applying the second divided signal to a first input of a second NAND gate of the generator circuit and applying a delayed first chopper signal to a second input of the second NAND gate to generate the second chopper signal.

### Claim 18 (depends on 1)

A system comprising the clock signal generator of claim 1.

### Claim 19 (depends on 18)

The system of claim 18, further comprising:
a transmission circuit coupled to the clock signal generator; and
a duty cycle distortion (DCD) corrector circuit coupled to the transmission circuit,
wherein the DCD corrector circuit is configured to correct DCD in the transmission circuit based on a code input to the DCD corrector circuit.