# US 11,442,484 B2 · Voltage regulator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,484 B2 - Document ID: US11442484B2 - Status: Granted - Kind: B2 - Application number: 17/241,268 - Filed: 2021-04-27 - Published: 2021-08-12 - Granted: 2022-09-13 - Earliest claimed: 2019-01-04 - Assignees: Silergy Semiconductor Technology (Hangzhou) LTD - Applicants: Silergy Semiconductor Technology (Hangzhou) LTD - Inventors: Wang Zhang; Chen Zhao; Lang Mao - Web page: https://patentgrep.com/patent/US11442484B2 ## CPC - G05F 3/10: using uncontrolled devices with non-linear characteristics - H02M 1/32: Means for protecting converters other than automatic disconnection - G05F 1/40: using discharge tubes or semiconductor devices as final control devices - G05F 1/46: wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A voltage regulator can include: an input port with two terminals, and being configured to receive an input voltage; an output port with two terminals, and being configured to generate an output voltage, where the input port and the output port have a common ground potential; a group of input switches coupled in series between the two terminals of the input port, where a common node of every two adjacent input switches that form an input half-bridge topology is taken as an input switch node; at least one output half-bridge topology coupled between two terminals of the output port, where a common node of a high-side output switch and a low-side output switch in each output half-bridge topology is taken as an output switch node; and N storage capacitors, where each of the storage capacitors is coupled between one input switch node and one output switch node. ## Claims ### Claim 1 A voltage regulator, comprising: a) an input port with two terminals, and being configured to receive an input voltage; b) an output port with two terminals, and being configured to generate an output voltage, wherein the input port and the output port have a common ground potential; c) at least one group of input switches coupled in series between the two terminals of the input port, wherein a common node of every two adjacent input switches in each group that form an input half-bridge topology is taken as an input switch node; d) at least one output half-bridge topology coupled between two terminals of the output port, wherein a common node of a high-side output switch and a low-side output switch in each output half-bridge topology is taken as an output switch node; and e) a plurality of storage capacitors, wherein each of the storage capacitors is coupled between one input switch node and one output switch node, such that each path from the input port to the output port comprises at least one storage capacitor. ### Claim 2 (depends on 1) The voltage regulator of claim 1, further comprising an output capacitor coupled between the two terminals of the output port to filter the output voltage. ### Claim 3 (depends on 1) The voltage regulator of claim 1, wherein the switching states of the two input switches that are coupled to the first terminal of a corresponding storage capacitor are correspondingly the same with the switching states of the two output switches in the output half-bridge topology coupled to the second terminal of the same corresponding storage capacitor. ### Claim 4 (depends on 3) The voltage regulator of claim 3, wherein the switching states of the high-side output switches and the low-side output switches are complementary. ### Claim 5 (depends on 1) The voltage regulator of claim 1, wherein duty cycles of the high-side output switches and the low-side output switches are the same, and there is a conduction phase difference between the high-side output switch and the low-side output switch in each output half-bridge topology. ### Claim 6 (depends on 5) The voltage regulator of claim 5, wherein the conduction phase difference between the high-side output switch and the low-side output switch is 180° . ### Claim 7 (depends on 3) The voltage regulator of claim 3, wherein when there are K groups of input switches, and the number of the input switches in each group is configured as 2N, N input half-bridge topologies are formed, and each common node of two input switches in each input half-bridge topology is taken as the input switch node, and the voltage regulator further comprises K×N input capacitors, each of which is coupled to two terminals of a corresponding input half-bridge topology, and the voltage regulator further comprises K×N storage capacitors having first terminals respectively coupled to different input switch nodes, wherein K and N are positive integers not less than 2. ### Claim 8 (depends on 7) The voltage regulator of claim 7, wherein when the switching states of the input switches in each group are correspondingly the same, the number of the output half-bridge topologies is configured as at least one, and each of the output switch nodes is coupled to at least one storage capacitor. ### Claim 9 (depends on 8) The voltage regulator of claim 8, wherein the high-side output switches are coupled to a positive terminal of the output port, and the low-side output switches are coupled to a negative terminal of the output port. ### Claim 10 (depends on 7) The voltage regulator of claim 7, wherein when the switching states of the input switches in L groups are respectively different and the switching states of the input switches in (K−L) groups are correspondingly the same, the number of the output half-bridge topologies is configured as at least (L+1), wherein L is less than K, and each of the output switch nodes is coupled to at least one storage capacitor. ### Claim 11 (depends on 7) The voltage regulator of claim 7, wherein when the switching states of the input switches in K groups are respectively different, the number of the output half-bridge topologies is configured as at least K, and each of the output switch nodes is coupled to at least one storage capacitor. ### Claim 12 (depends on 3) The voltage regulator of claim 3, wherein when there are K groups of input switches, and the number of the input switches in each group is configured as N+1, every two adjacent input switches form one input half-bridge topology, thereby forming N input switch nodes in each group of input switches, and the voltage regulator further comprises K×N storage capacitors having first terminals respectively coupled to different input switch nodes, wherein K and N are natural numbers not less than 2. ### Claim 13 (depends on 12) The voltage regulator of claim 12, wherein the number of the output half-bridge topology is not less than 2, and the output half-bridge topologies comprise at least one first-type output half-bridge topology and at least one second-type output half-bridge topology, and each of the output switch nodes is coupled to at least one storage capacitor, wherein the high-side output switch of the first-type output half-bridge topology is coupled to a positive terminal of the output port, and the low-side output switch of the second-type output half-bridge topology is coupled to a positive terminal of the output port. ### Claim 14 (depends on 13) The voltage regulator of claim 13, wherein the switching states of the input switches in each group are correspondingly the same. ### Claim 15 (depends on 13) The voltage regulator of claim 13, wherein high-side input switches in L groups are controlled by a first control signal, and high-side input switches in (K−L) groups are controlled by a second control signal, wherein the first and second control signal have a phase difference of 180° , and L is less than K. ### Claim 16 (depends on 12) The voltage regulator of claim 12, wherein when the switching states of the input switches in L groups are respectively different and the switching states of the input switches in (K−L) groups are correspondingly the same, the number of the output half-bridge topologies is configured as at least 2×(L+1), wherein L is less than K, and each of the output switch nodes is coupled to at least one storage capacitor. ### Claim 17 (depends on 12) The voltage regulator of claim 12, wherein when the switching states of the input switches in K groups are respectively different, the number of the output half-bridge topologies is configured as at least 2K, and each of the output switch nodes is coupled to at least one storage capacitor. ### Claim 18 (depends on 17) The voltage regulator of claim 17, wherein high-side input switches in each group are respectively controlled to be turned on with a phase difference of 360° /K. ### Claim 19 (depends on 1) The voltage regulator of claim 1, wherein each storage capacitor is further coupled in series with an inductor. ### Claim 20 (depends on 7) The voltage regulator of claim 7, wherein the switching states of the input switches and the output switches are controlled to be switched to control charging and discharging states of the storage capacitors, such that a ratio of the input voltage to the output voltage is N.