# US 11,442,107 B2 · System-on-chip for AT-SPEED test of logic circuit and operating method thereof

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- Number: US 11,442,107 B2
- Document ID: US11442107B2
- Status: Granted
- Kind: B2
- Application number: 17/206,288
- Filed: 2021-03-19
- Published: 2021-07-22
- Granted: 2022-09-13
- Earliest claimed: 2019-01-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Beom Seok Shin; Jinsoo Park
- Web page: https://patentgrep.com/patent/US11442107B2

## CPC

- G01R 31/318547: {Data generators or compressors}
- G01R 31/31712: {Input or output aspects}
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G01R 31/318569: {Error indication, logging circuits}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

## Claims

### Claim 1

A system-on-chip including a plurality of cores, comprising:
an input port;
a first scan register in a first core of the plurality of cores, the first scan register receiving scan data from the input port;
an inverting circuit on a feedback path of the first scan register; and
a logic circuit connected to an output terminal of the first scan register, wherein:
in a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting the scan data that are output from the first scan register,
the first scan register stores the test data in response to a first pulse of a clock signal, and
the logic circuit generates result data based on the test data that are output from the first scan register.

### Claim 2 (depends on 1)

The system-on-chip as claimed in claim 1, further comprising a second scan register in the first core,
wherein the second scan register stores the result data from the logic circuit, in response to a second pulse of the clock signal.

### Claim 3 (depends on 2)

The system-on-chip as claimed in claim 2, wherein a transition delay fault of the logic circuit is identified by comparing target data with the result data stored in the second scan register.

### Claim 4 (depends on 2)

The system-on-chip as claimed in claim 2, wherein the test mode for the AT-SPEED test of the logic circuit includes:
a first shift cycle in which the first scan register stores the scan data from the input port;
a capture cycle in which the second register stores the result data from the logic circuit; and
a second shift cycle in which the second register outputs the stored result data.

### Claim 5 (depends on 4)

The system-on-chip as claimed in claim 4, wherein the clock signal has a first frequency in the first shift cycle and the second shift cycle, and the clock signal has a second frequency different from the first frequency in the capture cycle.

### Claim 6 (depends on 5)

The system-on-chip as claimed in claim 5, wherein the first frequency is lower than the second frequency.

### Claim 7 (depends on 2)

The system-on-chip as claimed in claim 2, wherein the second pulse is adjacent to the first pulse.

### Claim 8 (depends on 1)

The system-on-chip as claimed in claim 1, wherein the test mode for the AT-SPEED test of the logic circuit includes:
a shift cycle in which the clock signal has a first frequency; and
a capture cycle in which the clock signal has a second frequency higher than the first frequency.

### Claim 9 (depends on 1)

The system-on-chip as claimed in claim 1, further comprising a selecting circuit to provide the first scan register with one of function data from the input port and the test data from the inverting circuit, wherein:
in the test mode, the selecting circuit selects the test data to provide the test data to the first scan register, and
the function data are provided from a top level core of the plurality of cores.

### Claim 10

A system-on-chip, comprising:
a first core including:
an output port;
a first scan register receiving scan data;
a first inverting circuit on a feedback path of the first scan register; and
a logic circuit connected between an output terminal of the first scan register and the output port; and
a second core including an input port connected to the output port of the first core, wherein:
in a test mode for an AT-SPEED test of the logic circuit, the first inverting circuit generates test data by inverting the scan data that are output from the first scan register,
the first scan register stores the test data in response to a first pulse of a clock signal, and
the logic circuit generates result data based on the test data that are output from the first scan register.

### Claim 11 (depends on 10)

The system-on-chip as claimed in claim 10, wherein:
the second core further includes a second scan register connected to the input port of the second core, and
the second scan register stores the result data from the logic circuit, in response to a second pulse of the clock signal.

### Claim 12 (depends on 11)

The system-on-chip as claimed in claim 11, wherein the test mode for the AT-SPEED test of the logic circuit includes:
a first shift cycle in which the first scan register stores the scan data;
a capture cycle in which the second register stores the result data from the logic circuit; and
a second shift cycle in which the second register outputs the stored result data.

### Claim 13 (depends on 12)

The system-on-chip as claimed in claim 12, wherein the clock signal has a first frequency in the first shift cycle and the second shift cycle, and the clock signal has a second frequency higher than the first frequency in the capture cycle.

### Claim 14 (depends on 10)

The system-on-chip as claimed in claim 10, wherein the second core is a top level core.

### Claim 15 (depends on 10)

The system-on-chip as claimed in claim 10, wherein:
the second core further includes:
a second scan register;
a second inverting circuit on a feedback path of the second scan register; and
a selecting circuit connected between the second scan register and the input port of the second core, the selecting circuit providing the second scan register with one of function data from the input port of the second core and test data from the second inverting circuit, and
the second scan register stores the one of the function data from the input port of the second core and the test data from the second inverting circuit, in response to a second pulse of the clock signal.

### Claim 16

An operating method of a system-on-chip including a first scan register, an inverting circuit, and a logic circuit, the method comprising:
outputting, by the first scan register, scan data in response to a clock signal having a first frequency;
providing the first scan register with test data generated by inverting the scan data that are output from the first scan register;
outputting, by the first scan register, the test data in response to a first pulse of the clock signal having a second frequency; and
outputting, by the logic circuit, result data based on the test data that are output from the first scan register.

### Claim 17 (depends on 16)

The method as claimed in claim 16, wherein the system-on-chip further includes a second scan register, the method further comprising:
outputting, by the second scan register, the result data in response to a second pulse of the clock signal having the second frequency.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein the second pulse is adjacent to the first pulse.

### Claim 19 (depends on 17)

The method as claimed in claim 17, wherein:
the system-on-chip includes a first core and a second core,
the first core includes the first scan register, the inverting circuit, the logic circuit, and an output port connected to the logic circuit, and
the second core includes the second scan register, and an input port connected to the output port of the first core.

### Claim 20 (depends on 19)

The method as claimed in claim 19, wherein the second core is a top level core.