# US 11,442,103 B2 · Multibit vectored sequential with scan > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,103 B2 - Document ID: US11442103B2 - Status: Granted - Kind: B2 - Application number: 17/240,877 - Filed: 2021-04-26 - Published: 2021-08-26 - Granted: 2022-09-13 - Earliest claimed: 2017-12-18 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Amit Agarwal; Ram Krishnamurthy; Satish Damaraju; Steven Hsu; Simeon Realov - Web page: https://patentgrep.com/patent/US11442103B2 ## CPC - G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)} - G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)} - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R 31/318541: {Scan latches or cell details} - H03K 3/0372: {of the primary-secondary type} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries. ## Claims ### Claim 1 An apparatus comprising: a first scan control input; a second scan control input; a scan input; a first tri-stateable inverter controllable by a buffered version of the first scan control input and an inverted version of the first scan control input, wherein the first tri-stateable inverter is to receive the scan input; a second tri-stateable inverter controllable by a buffered version of the second scan control input and an inverted version of the second scan control input, wherein the second tri-stateable inverter is to receive an output of the first tri-stateable inverter; a memory circuitry coupled to an output of the second tri-stateable inverter; a third tri-stateable inverter coupled to the memory circuitry and the output of the second tri-stateable inverter, wherein the third tri-stateable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input. ### Claim 2 (depends on 1) The apparatus of claim 1 comprising a pass-gate controllable by the buffered version of the first scan control input and the inverted version of the first scan control input, wherein the pass-gate is coupled to the output of the first tri-stateable inverter. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the pass-gate is part of a memory circuitry of a data path. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the memory circuitry of the data path includes: an inverter coupled to the pass-gate; a fourth tri-stateable inverter controllable by a clock and an inverse of the clock, wherein an input of the fourth tri-stateable inverter is coupled to the pass-gate, the first tri-stateable inverter, and the second tri-stateable inverter, and wherein an output of the fourth tri-stateable inverter is coupled to an input of the inverter. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the inverter is a first inverter, wherein the pass-gate is a first pass-gate, wherein the data path comprises: a second inverter to receive a data input; and a second pass-gate coupled to an output of the second inverter, wherein the second pass-gate is coupled to the first inverter and the fourth tri-stateable inverter, wherein the second pass-gate is controllable by the clock and the inverse of the clock. ### Claim 6 (depends on 1) The apparatus of claim 1 comprising: a fifth tri-stateable inverter controllable by the buffered version of the second scan control input and the inverted version of the second scan control input, wherein the fifth tri-stateable inverter is to receive an output of the third tri-stateable inverter. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the memory circuitry is a first memory circuitry, wherein the apparatus comprises: a second memory circuitry coupled to an output of the fifth tri-stateable inverter. ### Claim 8 (depends on 7) The apparatus of claim 7 comprising a sixth tri-stateable inverter coupled to the second memory circuitry and the output of the fifth tri-stateable inverter, wherein the sixth tri-stateable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input. ### Claim 9 An apparatus comprising: a processor circuitry; a memory coupled to the processor circuitry; a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes: a first circuitry including a first sequential circuitry and a second sequential circuitry; and a second circuitry to provide a scan of data associated with the first circuitry, wherein the second circuitry comprises a first bit-cell and a second bit-cell, wherein a portion of the first bit-cell of the second circuitry is part of a feedback path of the first sequential circuitry, and wherein a portion of the second bit-cell of the second circuitry is part of a feedback path of the second sequential circuitry. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein an output of the first bit-cell is coupled to an input of the second bit-cell. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the first comprises a clock buffer shared by the first and second sequential circuitries. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the feedback path of the first sequential circuitry comprises a latch. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the second comprises buffers to generate control signals, and wherein the buffers are shared by the first and second bit-cells. ### Claim 14 (depends on 9) The apparatus of claim 9, wherein the portion of the first bit-cell comprises a pass-gate. ### Claim 15 An apparatus comprising: a processor circuitry; a memory coupled to the processor circuitry; a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes: a first scan control input; a second scan control input; a scan input; a first tri-stateable inverter controllable by a buffered version of the first scan control input and an inverted version of the first scan control input, wherein the first tri-stateable inverter is to receive the scan input; a second tri-stateable inverter controllable by a buffered version of the second scan control input and an inverted version of the second scan control input, wherein the second tri-stateable inverter is to receive an output of the first tri-stateable inverter; a memory circuitry coupled to an output of the second tri-stateable inverter; a third tri-stateable inverter coupled to the memory circuitry and the output of the second tri-stateable inverter, wherein the third tri-stateable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input. ### Claim 16 (depends on 15) The apparatus of claim 15 comprising a pass-gate controllable by the buffered version of the first scan control input and the inverted version of the first scan control input, wherein the pass-gate is coupled to the output of the first tri-stateable inverter. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the pass-gate is part of a memory circuitry of a data path. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the memory circuitry of the data path includes: an inverter coupled to the pass-gate; a fourth tri-stateable inverter controllable by a clock and an inverse of the clock, wherein an input of the fourth tri-stateable inverter is coupled to the pass-gate, the first tri-stateable inverter, and the second tri-stateable inverter, and wherein an output of the fourth tri-stateable inverter is coupled to an input of the inverter. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the inverter is a first inverter, wherein the pass-gate is a first pass-gate, wherein the data path comprises: a second inverter to receive a data input; and a second pass-gate coupled to an output of the second inverter, wherein the second pass-gate is coupled to the first inverter and the fourth tri-stateable inverter, wherein the second pass-gate is controllable by the clock and the inverse of the clock. ### Claim 20 (depends on 19) The apparatus of claim 19 comprising: a fifth tri-stateable inverter controllable by the buffered version of the second scan control input and the inverted version of the second scan control input, wherein the fifth tri-stateable inverter is to receive an output of the third tri-stateable inverter. ### Claim 21 (depends on 20) The apparatus of claim 20, wherein the memory circuitry is a first memory circuitry, wherein the apparatus comprises: a second memory circuitry coupled to an output of the fifth tri-stateable inverter. ### Claim 22 (depends on 21) The apparatus of claim 21 comprising a sixth tri-stateable inverter coupled to the second memory circuitry and the output of the fifth tri-stateable inverter, wherein the sixth tri-stateable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input.