# US 11,442,091 B2 · Apparatus and methods for determination of capacitive and resistive characteristics of access lines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,091 B2 - Document ID: US11442091B2 - Status: Granted - Kind: B2 - Application number: 16/877,710 - Filed: 2020-05-19 - Published: 2021-07-01 - Granted: 2022-09-13 - Earliest claimed: 2019-12-27 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Dan Xu; Jun Xu; Erwin E. Yu - Web page: https://patentgrep.com/patent/US11442091B2 ## CPC - G01R 27/2605: {Measuring capacitance (capacitive sensors G01D5/24)} - G01R 27/08: Measuring resistance by measuring both voltage and current - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 29/025: {in signal lines} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/50008: {of impedance} - H04Q 9/00: Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) - H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W) ## Abstract Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells. ## Claims ### Claim 1 An apparatus, comprising: an array of memory cells; a plurality of access lines, wherein each access line of the plurality of access lines is connected to control gates of a respective plurality of memory cells of the array of memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to: apply a reference current to a selected access line of the plurality of access lines; identify a first event when a voltage level of a near end of the selected access line is deemed to exceed a first voltage level while applying the reference current; identify a second event when the voltage level of the near end of the selected access line is deemed to exceed a second voltage level, higher than the first voltage level, while applying the reference current; and determine a capacitance value of the selected access line in response to a current level of the reference current, a time difference between the second event and the first event, and a voltage difference between the second voltage level and the first voltage level. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller being configured to cause the apparatus to apply the reference current to the selected access line comprises the controller being configured to cause the apparatus to connect the selected access line to a current source. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the plurality of access lines is a plurality of local access lines, wherein the selected access line is a selected local access line of the plurality of local access lines, and wherein the controller being configured to cause the apparatus to connect the selected local access line to the current source comprises the controller being configured to cause the apparatus to connect the selected local access line to the current source through a particular global access line, wherein the particular global access line is selectively connected to the selected local access line and selectively connected to a different local access line of the plurality of local access lines. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the controller being configured to cause the apparatus to determine the capacitance value of the selected access line comprises the controller being configured to cause the apparatus to determine a first capacitance value of the selected access line while connected to the particular global access line and determine a second capacitance value while the particular global access line is isolated from the selected local access line, and determine a corrected capacitance value of the selected access line in response to the first capacitance value and the second capacitance value. ### Claim 5 (depends on 1) The apparatus of claim 1, further comprising: a comparator having a first input selectively connected to the near end of the selected access line, a second input connected to a voltage node configured to receive a variable reference voltage level, and an output; wherein the controller being configured to cause the apparatus to identify the first event when the voltage level of the near end of the selected access line is deemed to exceed the first voltage level comprises the controller being configured to cause the apparatus to: apply the first voltage level to the second input of the comparator while the first input of the comparator is connected to the selected access line; and determine when the output of the comparator makes a particular transition while applying the first voltage level to its second input. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the controller being configured to cause the apparatus to identify the second event when the voltage level of the near end of the selected access line is deemed to exceed the second voltage level comprises the controller being configured to cause the apparatus to: apply the second voltage level to the second input of the comparator while the first input of the comparator is connected to the selected access line; and determine when the output of the comparator makes the particular transition while applying the second voltage level to its second input. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the controller being configured to cause the apparatus to determine the capacitance value of the selected access line comprises the controller being configured to cause the apparatus to determine the capacitance value of the selected access line according to the equation Cwl=Iref*(t2−t1)/(V2−V1), where Cwl is the capacitance value of the selected access line, Iref is the current level of the reference current, t2 is a time of the second event, t1 is a time of the first event, V2 is the second voltage level, and V1 is the first voltage level. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the first voltage level and the second voltage level are selected such that a time difference between the second event and the first event is a multiple of an expected RC time constant of the selected access line. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the first voltage level and the second voltage level are selected such that the time difference between the second event and the first event is at least two times the expected RC time constant of the selected access line. ### Claim 10 An apparatus, comprising: an array of memory cells; a plurality of access lines, wherein each access line of the plurality of access lines is connected to control gates of a respective plurality of memory cells of the array of memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to: apply a reference current to a selected access line of the plurality of access lines; isolate the selected access line from the reference current in response to a voltage level of a near end of the selected access line being deemed to exceed a particular voltage level while applying the reference current; determine a resting voltage level of the selected access line after isolating the selected access line from the reference current; and determine a resistance value of the selected access line in response to a current level of the reference current and a voltage difference between the particular voltage level and the resting voltage level. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the controller being configured to cause the apparatus to apply the reference current to the selected access line comprises the controller being configured to cause the apparatus to connect the selected access line to a current mirror. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the plurality of access lines is a plurality of local access lines, wherein the selected access line is a selected local access line of the plurality of local access lines, and wherein the controller being configured to cause the apparatus to connect the selected local access line to the current mirror comprises the controller being configured to cause the apparatus to: activate a first transistor between the selected local access line and a particular global access line, wherein the particular global access line is further selectively connected to a different local access line of the plurality of local access lines through a second transistor; activate a third transistor between the particular global access line and a particular node; and activate a fourth transistor between the particular node and the current mirror. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the controller being configured to cause the apparatus to determine the resistance value of the selected access line comprises the controller being configured to cause the apparatus to determine a first resistance value of the selected access line while the first transistor is activated, determine a second resistance value while the first transistor is deactivated, and determine a corrected resistance value of the selected access line in response to the first resistance value and the second resistance value. ### Claim 14 (depends on 12) The apparatus of claim 12, further comprising: a comparator having a first input connected to the particular node, a second input connected to a voltage node configured to receive a variable reference voltage level, and an output; wherein the controller being configured to cause the apparatus to isolate the selected access line from the reference current in response to the voltage level of the near end of the selected access line being deemed to exceed the particular voltage level while applying the reference current comprises the controller being configured to cause the apparatus to: apply the particular voltage level to the second input of the comparator while the first transistor, the third transistor and the fourth transistor are each activated; determine when the output of the comparator makes a particular transition while applying the particular voltage level to its second input; and deactivating the fourth transistor in response to the output of the comparator making the particular transition while applying the particular voltage level to its second input. ### Claim 15 (depends on 10) The apparatus of claim 10, wherein the controller being configured to cause the apparatus to determine the resistance value of the selected access line comprises the controller being configured to cause the apparatus to determine the resistance value of the selected access line according to the equation Rwl=3*(V2−Vfinal)/Iref, where Rwl is the resistance value of the selected access line, Iref is the current level of the reference current, V2 is the second voltage level, and Vfinal is the resting voltage level. ### Claim 16 An apparatus, comprising: an array of memory cells; a plurality of access lines, wherein each access line of the plurality of access lines is connected to control gates of a respective plurality of memory cells of the array of memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to: apply a reference current to a selected access line of the plurality of access lines; identify a first event when a voltage level of a near end of the selected access line is deemed to exceed a first voltage level while applying the reference current; identify a second event when the voltage level of the near end of the selected access line is deemed to exceed a second voltage level, higher than the first voltage level, while applying the reference current; isolate the selected access line from the reference current in response to identifying the second event; determine a resting voltage level of the selected access line after isolating the selected access line from the reference current; determine a resistance value of the selected access line in response to a current level of the reference current and a voltage difference between the second voltage level and the resting voltage level; and determine a capacitance value of the selected access line in response to the current level of the reference current, a time difference between the second event and the first event, and a voltage difference between the second voltage level and the first voltage level. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the plurality of access lines is a plurality of local access lines, wherein the selected access line is a selected local access line of the plurality of local access lines, and wherein the controller being configured to cause the apparatus to apply the reference current to the selected local access line comprises the controller being configured to cause the apparatus to: activate a first transistor between the selected local access line and a particular global access line, wherein the particular global access line is further selectively connected to a different local access line of the plurality of local access lines through a second transistor; activate a third transistor between the particular global access line and a particular node; and activate a fourth transistor between the particular node and a current source generating the reference current. ### Claim 18 (depends on 17) The apparatus of claim 17, further comprising: a comparator having a first input connected to the particular node, a second input connected to a voltage node configured to receive a variable reference voltage level, and an output; wherein the controller being configured to cause the apparatus to identify the second event when the voltage level of the near end of the selected access line is deemed to exceed the second voltage level comprises the controller being configured to cause the apparatus to: apply the second voltage level to the voltage node while the first transistor, the third transistor and the fourth transistor are each activated; and determine when the output of the comparator makes a particular transition while applying the second voltage level to the voltage node. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the controller being configured to cause the apparatus to determine the resting voltage level of the selected access line comprises the controller being configured to cause the apparatus to: decrease the voltage level applied to the voltage node while the fourth transistor is deactivated, and while the first transistor and the third transistor are each activated; and determine when the output of the comparator makes a different transition while applying the second voltage level to the voltage node. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the controller being configured to cause the apparatus to decrease the voltage level applied to the voltage node comprises the controller being configured to cause the apparatus to decrement the voltage level applied to the voltage node.