# US 11,442,082 B2 · Droop detection

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- Number: US 11,442,082 B2
- Document ID: US11442082B2
- Status: Granted
- Kind: B2
- Application number: 17/082,667
- Filed: 2020-10-28
- Published: 2021-06-24
- Granted: 2022-09-13
- Earliest claimed: 2019-12-23
- Assignees: Graphcore Limited
- Applicants: Graphcore Limited
- Inventors: Stephen Felix; Daniel John Pelham Wilkinson
- Web page: https://patentgrep.com/patent/US11442082B2

## CPC

- G01R 19/16504: {characterised by the components employed}
- G01R 17/02: Arrangements in which the value to be measured is automatically compared with a reference value
- G01R 19/16552: {in I.C. power supplies}
- G01R 19/2513: {Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging}
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- H03K 5/14: by the use of delay lines (H03K5/133 takes precedence)
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.

## Claims

### Claim 1

A method for detecting voltage droop in a supply voltage for a processor, the method comprising:
receiving at a tap sampled delay line, a first clock signal, wherein the tap sampled delay line is powered by a same power supply that supplies the supply voltage to the processor;
splitting the first clock signal along two different paths in the tap sampled delay line;
producing a set of samples of the first clock signal by, along each of the two different paths, upon receipt of an edge of a sample clock signal, sampling the first clock signal at each of a set of taps in the respective path, wherein each of the taps in the respective path is separated by two inverter delays such that the set of samples represent sample values of the first clock signal each separated by a single inverter delay without inversion of the first clock signal between the samples; and
determining a magnitude of the voltage droop by measuring from the set of samples, a change in a clock edge position of the first clock signal,
wherein the sample clock signal has a same frequency as the first clock signal, and wherein the first clock signal is also received from a further delay line, wherein the further delay line has coarser delay stages than the tap sampled delay line to delay the first clock signal by an amount such that, when a rising edge of the sample clock signal arrives at the tap sampled delay line, a previous rising edge of the sample clock signal is located in the tap sampled delay line.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the first clock signal is a delayed version of the sample clock signal.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein the tap sampled delay line comprises a plurality of connections between the two different paths for limiting drift of the first clock signal between the two different paths, wherein each of the connections comprises at least one inverter.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein each of the set of taps comprises a pair of flip flops, wherein each pair of flip flops comprises:
a first flip flop for sampling the first clock signal to latch a value in response to receipt of the edge of the sample clock signal; and
a second flip flop for sampling an output of the first flip flop in response to receipt of a subsequent edge of the sample clock signal.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the step of determining the magnitude of the voltage droop comprises:
determining an average clock edge position for the first clock signal in the tap sampled delay line; and
determining a deviation in the clock edge position from the average clock edge position.

### Claim 6 (depends on 1)

The method as claimed in claim 1, further comprising:
receiving from a clock generator, a first processor clock signal for supplying to the processor, the first processor clock signal being of a first frequency;
in response to detecting the voltage droop, generating a second processor clock signal of a second frequency, wherein the second frequency is lower than the first frequency; and
providing the second processor clock signal to the processor.

### Claim 7 (depends on 6)

The method as claimed in claim 6, wherein the step of generating the second processor clock signal comprises removing a proportion of clock pulses from the first processor clock signal.

### Claim 8 (depends on 7)

The method as claimed in claim 7, wherein the method comprises, following the step of removing the proportion of clock pulses from the first processor clock signal, adjusting the second processor clock signal so as to increase the second frequency, the adjusting the second processor clock signal comprising decreasing the proportion of clock pulses removed from the first processor clock signal.

### Claim 9 (depends on 6)

The method as claimed in claim 6, wherein the step of generating the second processor clock signal comprises:
determining that the voltage droop exceeds a threshold; and
in response to determining that the voltage droop exceeds the threshold, generating the second processor clock signal.

### Claim 10 (depends on 6)

The method as claimed in claim 6, comprising:
receiving the second processor clock signal at the processor; and
propagating the second processor clock signal along copper wires of the processor for clocking a plurality of components of the processor.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the copper wires have a thickness of greater than 0.2 micrometres.

### Claim 12 (depends on 10)

The method as claimed in claim 10, wherein the plurality of components of the processor comprises a plurality of processing units.

### Claim 13

An apparatus for detecting voltage droop in a supply voltage for a processor, the apparatus comprising a tap sampled delay line comprising:
an input for receiving at the tap sampled delay line, a first clock signal, wherein the tap sampled delay line is powered by a same power supply that supplies the supply voltage to the processor;
two different clock paths, each configured to propagate the first clock signal as a differential clock signal;
a plurality of taps arranged along each of the two different clock paths in the tap sampled delay line, the plurality of taps configured to produce a set of samples of the first clock signal by sampling the first clock signal, wherein along each of the different clock paths, each of the taps in a respective path is separated by at least two inverter delays; and
circuitry configured to determine a magnitude of the voltage droop by measuring a change in a clock edge position of the first clock signal from the set of samples,
wherein a sample clock signal has a same frequency as the first clock signal, wherein the apparatus comprises a further delay line having coarser delay stages than the tap sampled delay line, wherein the tap sampled delay line is configured to receive the first clock signal from the further delay line, and wherein the further delay line is configured to delay the first clock signal by an amount such that, when a rising edge of the sample clock signal arrives at the tap sampled delay line, a previous rising edge of the sample clock signal is located in the tap sampled delay line.

### Claim 14 (depends on 13)

The apparatus as claimed in claim 13, wherein the apparatus comprises clock signal modification circuitry configured to:
receive from a clock generator, a first processor clock signal for supplying to the processor, the first processor clock signal being of a first frequency;
generate a second processor clock signal of a second frequency, wherein the second frequency is lower than the first frequency; and
provide the second processor clock signal to the processor.

### Claim 15 (depends on 14)

The apparatus as claimed in claim 14, wherein the generating the second processor clock signal comprises removing a proportion of clock pulses from the first processor clock signal.

### Claim 16 (depends on 14)

The apparatus as claimed in claim 14, comprising the processor configured to:
receive the second processor clock signal; and
propagate the second processor clock signal along copper wires of the processor for clocking one or more components of the processor.

### Claim 17

A method for determining a magnitude of voltage droop in a supply voltage for a processor, the method comprising:
receiving a first clock signal at a tap sampled delay line that is powered by a same power supply that supplies the supply voltage to the processor;
splitting the first clock signal along a first path in the tap sampled delay line and a second path in the tap sampled delay line;
producing a set of samples of the first clock signal along the first path and the second path, including sampling the first clock signal at a plurality of taps in the first path and the second path, wherein each tap of the plurality of taps is separated by two inverter delays; and
measuring a change in a clock edge position of the first clock signal from the set of samples,
wherein a sample clock signal has a same frequency as the first clock signal, wherein the first clock signal is also received from a further delay line, wherein the further delay line has coarser delay stages than the tap sampled delay line to delay the first clock signal by an amount such that, when a rising edge of the sample clock signal arrives at the tap sampled delay line, a previous rising edge of the sample clock signal is located in the tap sampled delay line.