# US 11,440,051 B2 · Capacitive micromachined ultrasonic transducer (CMUT) devices and methods of manufacturing

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- Number: US 11,440,051 B2
- Document ID: US11440051B2
- Status: Granted
- Kind: B2
- Application number: 16/802,345
- Filed: 2020-02-26
- Published: 2021-08-26
- Granted: 2022-09-13
- Earliest claimed: 2020-02-26
- Assignees: General Electric Company
- Applicants: General Electric Company
- Inventors: Yizhen Lin; Marco Francesco Aimi; Alessandro Stuart Savoia
- Web page: https://patentgrep.com/patent/US11440051B2

## CPC

- B06B 1/0292: {Electrostatic transducers, e.g. electret-type}
- B81B 3/0021: {Transducers for transforming electrical into mechanical energy or vice versa (dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00)}
- B81C 1/00357: {involving bonding one or several substrates on a non-temporary support, e.g. another substrate}
- B81B 2201/0271: Resonators; ultrasonic resonators
- B81B 2203/0127: Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
- B81B 2207/012: the micromechanical device and the control or processing electronics being separate parts in the same package
- B81B 2207/07: Interconnects
- B81C 2201/0125: Blanket removal, e.g. polishing
- B81C 2201/0132: Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
- B81C 2201/0194: the layer being structured
- B81C 2203/0109: Bonding an individual cap on the substrate
- B81C 2203/0792: Forming interconnections between the electronic processing unit and the micromechanical structure
- B06B: METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, {e.g.} FOR PERFORMING MECHANICAL WORK IN GENERAL (for particular applications, see the relevant subclasses, e.g. B07B1/40, B23Q17/12, B24B31/06; measurement of mechanical vibrations G01H; in direction finding, locating, distance or velocity measuring G01S; {generating seismic energy G01V1/02}; control of mechanical vibrations in general G05D; sound-producing devices, e.g. bells, sirens, whistles G10K, {e.g. methods or devices for transmitting, conducting, or directing sound in general G10K11/00}; generation of electrical oscillations H03B; electromechanical resonators in general H03H; electromechanical transducers {for communication techniques, e.g. microphones, speakers} H04R)
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)

## Abstract

A method of forming a capacitive micromachined ultrasonic transducer (CMUT) device includes bonding a CMUT substrate to a silicon on insulator (SOI) substrate. The CMUT substrate has a first thickness and the SOI substrate includes a handle, a buried oxide layer, and a device layer. At least one of the CMUT substrate or the SOI substrate includes a patterned dielectric layer. The device layer is bonded to the patterned dielectric layer to form a plurality of sealed cavities and the device layer forms a diaphragm of the plurality of cavities. The method further includes reducing the first thickness of the CMUT substrate to a second thickness and forming a plurality of through-silicon vias from a second surface of the CMUT substrate opposite the first surface.

## Claims

### Claim 1

A method of forming a capacitive micromachined ultrasonic transducer (CMUT) device, comprising:
bonding a CMUT substrate to a silicon on insulator (SOI) substrate, the CMUT substrate having a first thickness, the SOI substrate including a handle, a buried oxide layer, and a device layer, at least one of the CMUT substrate or the SOI substrate including a patterned dielectric layer, wherein the device layer is bonded to the patterned dielectric layer to form a plurality of sealed cavities and the device layer forms a diaphragm of the plurality of cavities;
reducing the first thickness of the CMUT substrate to a second thickness; and
forming a plurality of through-silicon vias from a second surface of the CMUT substrate opposite a first surface.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a second dielectric layer on the second surface.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a plurality of metal bond posts through and on the second dielectric layer.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
attaching a CMOS device to the metal bond posts.

### Claim 5 (depends on 2)

The method of claim 2, further comprising:
removing portions of the handle and buried oxide layer of the SOI substrate, wherein removed portions of the handle and the buried oxide layer form channels in the SOI substrate, the channels exposing the diaphragm and being separated from the sealed cavities by the diaphragm.

### Claim 6 (depends on 5)

The method of claim 5, wherein the channels are between 300 μm and 500 μm in length.

### Claim 7 (depends on 5)

The method of claim 5, further comprising:
etching a portion of the diaphragm and a portion of the first dielectric layer to form a contact area; and
forming a metal layer over the diaphragm and a portion of the first dielectric layer to form a contact.

### Claim 8 (depends on 3)

The method of claim 3, wherein a diameter of the bond posts is between 10 μm and 40 μm and a height of the bond posts is between 1 μm and 20 μm.

### Claim 9 (depends on 3)

The method of claim 3, further comprising:
attaching a glass substrate having a plurality of metal vias formed through the glass substrate and on a surface of the glass substrate to the metal bond posts.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
removing the handle and buried oxide layer from the SOI substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the handle is removed after attaching the glass substrate.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
etching a portion of the diaphragm and a portion of the first dielectric layer to form a contact area; and
forming a metal layer over the diaphragm and a portion of the first dielectric layer to form a contact.

### Claim 13 (depends on 3)

The method of claim 3, wherein the bond posts are formed in a center of each cell of the CMUT device and in a polygonal arrangement around the center of each cell of the CMUT device.

### Claim 14 (depends on 1)

The method of claim 1, further comprising:
forming a plurality of metal bond posts directly on the second surface.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
attaching a CMOS device to the metal bond posts.

### Claim 16 (depends on 1)

The method of claim 1, further comprising:
prior to reducing the first thickness of the CMUT substrate to the second thickness, removing the handle and the buried oxide layer from the SOI substrate;
etching a portion of the diaphragm and a portion of the first dielectric layer to form a contact area;
forming a metal layer over the diaphragm and a portion of the first dielectric layer to form a contact; and
bonding a cap to the CMUT substrate on the first surface over the diaphragm and metal layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
removing the cap from the CMUT substrate.

### Claim 18 (depends on 1)

The method of claim 1, wherein the first thickness is between 300 μm and 750 μm and the second thickness is between 20 μm and 50 μm.

### Claim 19 (depends on 18)

The method of claim 18, wherein the second thickness is 30 μm.

### Claim 20 (depends on 1)

A CMUT device manufactured according to the method of claim 1.