Package with substrate comprising variable thickness solder resist layer

A package comprising:

• a substrate comprising:
• at least one dielectric layer;
• a plurality of interconnects located in the at least one dielectric layer;
• a solder resist layer located over a surface of the at least one dielectric layer, wherein the solder resist layer comprises:
• a first solder resist layer portion comprising a first thickness;
• a second solder resist layer portion comprising a second thickness that is less than the first thickness;
• a first cavity in the solder resist layer,
• wherein the first cavity has a first width, and
• wherein the first cavity is located over the second solder resist layer portion,
• a third solder resist layer portion comprising a third thickness that is less than the first thickness;
• and
• a second cavity in the solder resist layer,
• wherein the second cavity has a second width, and
• wherein the second cavity is located over the third solder resist layer portion;
• a first electrical component coupled to the substrate, wherein the first electrical component is located over the second solder resist layer portion and the first cavity in the solder resist layer, wherein the first width of the first cavity in the solder resist layer is greater than a width of the first electrical component;
• a second electrical component coupled to the substrate, wherein the second electrical component is located over the third solder resist layer portion and the second cavity in the solder resist layer, wherein the second width of the second cavity in the solder resist layer is greater than a width of the second electrical component;
• and
• an encapsulation layer coupled to the substrate,
• wherein the encapsulation layer is located over the substrate, the first electrical component and the second electrical component, and
• wherein the encapsulation layer is further located (i) between the first electrical component and the substrate, and (ii) between the second electrical component and the substrate.

A method for fabricating a substrate, comprising:

• forming at least one dielectric layer;
• forming a plurality of interconnects in the at least one dielectric layer;
• forming a first plurality of surface interconnects on a surface of the at least one dielectric layer, wherein forming the first plurality of surface interconnects includes forming a first surface interconnect comprising a first width;
• forming a second plurality of surface interconnects on a surface of the at least one dielectric layer, wherein forming the second plurality of surface interconnects includes forming a second surface interconnect comprising a second width;
• and
• forming a solder resist layer over a surface of the at least one dielectric layer, wherein forming the solder resist layer comprises:
• forming a first solder resist layer portion comprising a first thickness in a range of about 12-15 micrometers;
• forming a second solder resist layer portion comprising a second thickness that is less than the first thickness, wherein the second solder resist layer portion has a width that is greater than first width of the first surface interconnect, wherein the second thickness is in a range of about 1-12 micrometers;
• and
• forming a third solder resist layer portion comprising a third thickness that is less than the first thickness, wherein the third solder resist layer portion has a width that is greater than second width of the second surface interconnect, wherein the second thickness is in a range of about 1-12 micrometers.