Phase detection method, phase detection circuit, and clock recovery apparatus
AssigneeHuawei Technologies Co., Ltd.
InventorYuchun Lu
Life of this patent
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Abstract
Embodiments of this application disclose example phase detection methods, phase detection circuits, and clock recovery apparatuses. One example method includes receiving a first signal and deciding a (2M−1) level of the first signal to obtain a decision result, where the first signal is a (2M−1)-level signal, and M is a positive integer. A response amplitude parameter of a transmission channel can then be obtained. Clock phase information in the first signal can then be extracted based on the first signal, the decision result, and the response amplitude parameter. Output clock phase information can then be determined based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods.
Claims8
A phase detection method, applied to a phase detection circuit, wherein the method comprises:
- receiving, by the phase detection circuit, a first signal and deciding a (2M−1) level of the first signal to obtain a decision result, wherein the first signal is a (2M−1)-level signal, and M is a positive integer greater than 1;
- obtaining a response amplitude parameter of a transmission channel;
- obtaining a phase offset parameter, wherein the phase offset parameter is used to tune clock phase information in the first signal;
- extracting the clock phase information in the first signal based on the first signal, the decision result, the response amplitude parameter, and the phase offset parameter;
- and
- determining output clock phase information based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods, wherein the at least three pieces of clock phase information comprises the clock phase information in the first signal.
A phase detection circuit, wherein the circuit comprises:
- a receiver of the phase detection circuit, configured to receive a first signal, wherein the first signal is a (2M−1)-level signal, and M is a positive integer greater than 1;
- at least one processor;
- and
- a non-transitory computer-readable storage medium coupled to the at least one processor and storing programming instructions for execution by the at least one processor, wherein the programming instructions instruct the at least one processor to:
- decide a (2M−1) level of the first signal to obtain a decision result;
- obtain a response amplitude parameter of a transmission channel;
- obtaining a phase offset parameter, wherein the phase offset parameter is used to tune clock phase information in the first signal;
- extract the clock phase information in the first signal based on the first signal, the decision result, the response amplitude parameter, and the phase offset parameter;
- and
- determine output clock phase information based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods, wherein the at least three pieces of clock phase information comprises the clock phase information in the first signal.
A non-transitory computer-readable storage medium storing program instructions, and wherein when the program instructions are executed by at least one processor, the program instructions instruct the at least one processor to:
- receive, by a phase detection circuit, a first signal and decide a (2M 1) level of the first signal to obtain a decision result, wherein the first signal is a (2M 1) level signal, and M is a positive integer greater than 1;
- obtain a response amplitude parameter of a transmission channel;
- obtain a phase offset parameter, wherein the phase offset parameter is used to tune clock phase information in the first signal;
- extract the clock phase information in the first signal based on the first signal, the decision result, the response amplitude parameter, and the phase offset parameter;
- and determine output clock phase information based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods, wherein the at least three pieces of clock phase information comprises the clock phase information in the first signal.
Dependencies are inferred from the claim text.