# US 11,432,715 B2 · System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects

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- Number: US 11,432,715 B2
- Document ID: US11432715B2
- Status: Granted
- Kind: B2
- Application number: 17/088,502
- Filed: 2020-11-03
- Published: 2021-02-18
- Granted: 2022-09-06
- Earliest claimed: 2011-05-12
- Assignees: DePuy Synthes Products, Inc.
- Applicants: DePuy Synthes Products, Inc.
- Inventors: Laurent Blanquart
- Web page: https://patentgrep.com/patent/US11432715B2

## CPC

- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- A61B 1/00009: {of image signals during a use of endoscope}
- A61B 1/051: {Details of CCD assembly}
- A61B 1/0676: {at distal tip of an endoscope}
- H04N 23/56: provided with illuminating means
- H04N 25/767: Horizontal readout lines, multiplexers or registers
- H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N 25/79: Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10F 39/014: {of CMOS image sensors}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/12: Image sensors
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H10F 39/804: {Containers or encapsulations}
- H10F 39/809: {of hybrid image sensors}
- H10F 39/811: {Interconnections}
- H10F 39/812: {Arrangements for transferring the charges in the image sensor perpendicular to the imaging plane, e.g. buried regions used to transfer generated charges to circuitry under the photosensitive region}
- H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 90/00: Package configurations
- H04N 23/555: {for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes}
- H10F 77/122: comprising only Group IV materials
- H10F 77/123: comprising only Group II-VI materials, e.g. CdS, ZnS or HgCdTe
- H10F 77/124: comprising only Group III-V materials, e.g. GaAs
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- A61B: DIAGNOSIS; SURGERY; IDENTIFICATION (usefulness limited to only animals A61D)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.

## Claims

### Claim 1

An imaging sensor comprising:
a pixel array comprising a plurality of pixel columns disposed on a first substrate, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;
a plurality of supporting circuits disposed on one or more additional substrates, the plurality of supporting circuits comprising a plurality of circuit columns, wherein each of the plurality of circuit columns is divided into a plurality of circuit sub-columns; and
a plurality of interconnects for electrically connecting each pixel sub-column to one of the plurality of circuit sub-columns;
wherein each of the plurality of circuit sub-columns has an area, a size, and an aspect ratio, and each of the plurality of pixel sub-columns that corresponds to each one of the circuit sub-columns has an area, a size, and an aspect ratio; and
wherein the aspect ratio of at least one of the circuit sub-columns has a width equal to “N” times the width of the aspect ratio of one of said pixel sub-columns and a length equal to 1/“N” times the length of the aspect ratio of one of said pixel sub-columns.

### Claim 2 (depends on 1)

The imaging sensor of claim 1, wherein the one or more additional substrates are disposed remotely relative to the first substrate.

### Claim 3 (depends on 1)

The imaging sensor of claim 1, further comprising a pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate and a circuit sub-column bus for each of the plurality of circuit sub-columns on the one or more additional substrates.

### Claim 4 (depends on 3)

The imaging sensor of claim 3, wherein each pixel sub-column bus on the first substrate is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates, wherein the first substrate and the one or more additional substrates are in a stacked configuration.

### Claim 5 (depends on 4)

The imaging sensor of claim 4, wherein at least one interconnect of the plurality of interconnects electrically connects each pixel sub-column to one of the plurality of circuit sub-columns by connecting the pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate with a corresponding circuit sub-column bus for each of the plurality of circuit sub-columns on the one or more additional substrates.

### Claim 6 (depends on 3)

The imaging sensor of claim 3, wherein electrical communication between the pixel sub-column bus and a corresponding circuit sub-column bus is provided by the interconnect such that each of the pixel sub-columns is read independently.

### Claim 7 (depends on 1)

The imaging sensor of claim 1, wherein each pixel sub-column is electronically isolated from other pixel sub-columns.

### Claim 8 (depends on 1)

The imaging sensor of claim 1, wherein each circuit sub-column is dedicated to one of the plurality of pixel sub-columns of the pixel array.

### Claim 9 (depends on 1)

The imaging sensor of claim 1, wherein the plurality of supporting circuits in each of the circuit sub-columns are configured to independently read and process data from a corresponding pixel sub-column, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.

### Claim 10 (depends on 1)

The imaging sensor of claim 1, wherein the area of one of said pixel sub-columns is substantially equal to the area of one of said corresponding circuit sub-columns.

### Claim 11 (depends on 1)

The imaging sensor of claim 1, wherein the size of one of said pixel sub-columns is substantially equal to the size of one of said corresponding circuit sub-columns.

### Claim 12 (depends on 1)

The imaging sensor of claim 1, wherein the area of one of said pixel sub-columns is different than the area of one of said corresponding circuit sub-columns.

### Claim 13 (depends on 1)

The imaging sensor of claim 1, wherein the size of one of said pixel sub-columns is different to the size of one of said corresponding circuit sub-columns.

### Claim 14 (depends on 1)

The imaging sensor of claim 1, wherein the aspect ratio of one of said pixel sub-columns is substantially similar to the aspect ratio of one of said corresponding circuit sub-columns.

### Claim 15 (depends on 1)

The imaging sensor of claim 1, wherein the aspect ratio of one of said pixel sub-columns is different from the aspect ratio of one of said corresponding circuit sub-columns.

### Claim 16 (depends on 1)

The imaging sensor of claim 1, wherein each of the plurality of interconnects is positioned at a distance that is at least two pixel widths away from any other interconnects of the plurality of interconnects.

### Claim 17 (depends on 1)

The imaging sensor of claim 1, wherein said plurality of interconnects are spaced relative to one another at a distance that is greater than a pixel pitch of said pixel array.