Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition

An apparatus, comprising:

• a phase locked loop (PLL) configured to generate a reference signal;
• a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal;
• a first pre-charge circuit connected to a sampling device of the SS-PLL, the first pre-charge circuit configured to facilitate frequency locking of the SS-PLL;
• a frequency locking loop (FLL) connected to the SS-PLL;
• a switch connected between the FLL and an output of the SS-PLL;
• and
• a coarse tuner connected between the output of the SS-PLL and an input of the SS-PLL to implement coarse tuning in the FLL loop before pre-charging by the first pre-charge circuit for frequency locking of the SS-PLL.

A method, comprising:

• generating, by a phase locked loop (PLL), a reference signal;
• sub-sampling, by a sub-sampling PLL (SS-PLL) connected to the PLL, the reference signal;
• and
• causing frequency locking of the SS-PLL, by a first pre-charge circuit connected between a sampling device of the SS-PLL and a first power supply voltage;
• and
• pre-charging an output voltage of the SS-PLL, by a second pre-charge circuit connected between the sampling device and a second power supply voltage.

A method, comprising:

• generating, by a phase locked loop (PLL), a reference signal;
• sub-sampling, by a sub-sampling PLL (SS-PLL) connected to the PLL, the reference signal;
• causing frequency locking of the SS-PLL, by a first pre-charge circuit connected to a sampling device of the SS-PLL;
• locking, by a frequency locking loop (FLL) connected to the SS-PLL, a frequency of the SS-PLL;
• switching, by a switch connected between the FLL and an output of the SS-PLL, the output of the SS-PLL to the FLL;
• and
• coarse tuning, by a coarse tuner connected between the output of the SS-PLL and an input of the SS-PLL, the SS-PLL, wherein coarse tuning is implemented in the FLL loop before pre-charging by the first pre-charge circuit for frequency locking of the SS-PLL.