Conversion and folding circuit for delay-based analog-to-digital converter system

A comparison and folding circuit operable to be implemented in an analog-to-digital converter, the comparison and folding circuit comprising:

• a plurality of comparators each having a first input coupled to a input voltage (VIN), a second input, a first output and a second output, the second input of each of the plurality of comparators is adapted to be coupled to a different reference voltage;
• a first plurality of AND gates each having a first input coupled to the first output of a corresponding one of the plurality of comparators, a second input coupled to the second output of the corresponding one of the plurality of comparators and an output;
• and
• a first plurality of OR gates each having a first input coupled to the first output of a corresponding one of the plurality of comparators, a second input coupled to the second output of the corresponding one of the plurality of comparators and an output.