Package structure and method of fabricating the same

A package structure, comprising:

• a circuit substrate;
• an interposer structure disposed on the circuit substrate, wherein the interposer structure includes a core substrate and a plurality of through vias formed in the core substrate, wherein the core substrate of the interposer structure comprises a beveled portion with a first beveled surface;
• at least one semiconductor die disposed on a backside surface of the interposer structure, wherein the at least one semiconductor die is electrically connected to the plurality of through vias;
• an insulating encapsulant disposed on the backside surface of the interposer structure and surrounding the at least one semiconductor die, wherein the insulating encapsulant comprises a beveled top surface that is aligned with the first beveled surface;
• a polymer layer disposed on a top surface of the interposer structure, wherein the polymer layer comprises a central portion and a flank portion connected to the central portion, the central portion comprises conductive elements embedded therein, and the conductive elements is in direct contact with the plurality of through vias of the interposer structure, while the central portion of the polymer layer is covering and in contact with the top surface of the interposer structure, the flank portion protrudes out from the central portion and is surrounding the interposer structure, and wherein the flank portion has a sloped surface that is covering and in direct contact with the first beveled surface and the beveled top surface, and a side surface of the flank portion is aligned with a side surface of the insulating encapsulant.

A method of fabricating a package structure, comprising:

• forming a semiconductor device, comprising:
• providing an interconnection structure having a device region and a dicing region surrounding the device region, and the interconnection structure is formed with a semiconductive first material that has a first CTE value;
• disposing a semiconductor die on a first surface of the interconnection structure within the device region, wherein the semiconductor die is electrically connected to the interconnection structure;
• forming a first trench on the first surface of the interconnection structure within the dicing region, wherein the first trench surrounds the semiconductor die;
• forming an insulating encapsulant over the device region and the dicing region on the first surface of the interconnection structure, wherein the insulating encapsulant encapsulates the semiconductor die and fills into the first trench;
• performing a first dicing process by removing portions of the interconnection structure and portions of the insulating encapsulant to form a second trench on a second surface of the interconnection structure in the dicing region, the second surface being opposite to the first surface;
• forming a protection layer over the device region and the dicing region on the second surface of the interconnection structure, wherein the protection layer fills into the second trench and is in contact with the insulating encapsulant, the protection layer is made of a second material that has a second CTE value, wherein the second CTE value is a value within a second range, and the second range is non-overlapped with the first CTE value;
• forming a plurality of electrical connectors on the protection layer, wherein the plurality of electrical connectors is electrically connected to the interconnection structure;
• performing a second dicing process by cutting through the protection layer and the insulating encapsulant, wherein the insulating encapsulant partially covers sidewalls of the interconnection structure and the protection layer partially covers the sidewalls of the interconnection structure after the second dicing process;
• disposing the semiconductor device on a circuit substrate, wherein the semiconductor device is electrically connected to the circuit substrate through the plurality of electrical connectors;
• and
• forming an underfill structure in between the circuit substrate and the semiconductor device, wherein the underfill structure covers the plurality of electrical connectors and is in contact with the insulating encapsulant and the protection layer, wherein the underfill structure is made of a third material different from the second material, and having a third CTE value, wherein the third CTE value is a value within a third range, and the third range is overlapped with the second range.