US 11,423,967 B1 · Stacked ferroelectric non-planar capacitors in a memory bit-cell

Abstract

A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Claims20

Dependent claims

An apparatus comprising:

a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, wherein the via couples to a first metal layer;
a first non-planar stack of materials including a non-linear polar material, wherein the first non-planar stack of materials includes an electrode coupled to the via, wherein the electrode is in a middle of the first non-planar stack of materials;
a second non-planar stack of materials including the non-linear polar material, wherein the electrode passes through a middle of the second non-planar stack of materials;
a first plate-line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, wherein the first plate-line is on a portion of the first non-planar stack of materials;
and
a second plate-line extending along the x-plane or the z-plane, wherein the second plate-line is on a portion of the second non-planar stack of materials.

3 more elements

An apparatus comprising:

a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, wherein the via couples to a first metal layer;
a first capacitor including a non-linear polar material, wherein the first capacitor includes am electrode coupled to the via, wherein the electrode is in a middle of the first capacitor;
a second capacitor including the non-linear polar material, wherein the electrode passes through a middle of the second capacitor;
a first plate-line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, wherein the first plate-line is on an outer portion of the first capacitor;
and
a second plate-line extending along the x-plane or the z-plane, wherein the second plate-line is on an output portion of the second capacitor.

3 more elements

Dependencies are inferred from the claim text.

Stacked ferroelectric non-planar capacitors in a memory bit-cell

Life of this patent

Stacked ferroelectric non-planar capacitors in a memory bit-cell

Life of this patent

Abstract

Claims20