Suspect resolution for scan chain defect diagnosis

A system comprising:

• a memory system configured to store computer-executable instructions;
• and
• a computing system, in response to execution of the computer-executable instructions, is configured to:
• perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains;
• determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains;
• and
• generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• performing, by a computing system, fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains;
• determining, by the computing system, locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains;
• and
• generating, by the computing system, a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.