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US 11,422,885 B2Granted
Tiered error correction code (ECC) operations in memory
AssigneeMicron Technology, Inc.
InventorsMustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy
Life of this patent
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Abstract
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
Claims17
A method, comprising:
- performing a first error code correction (ECC) operation on data read from a memory array, wherein the first ECC operation uses hard data to correct errors in the data;
- and
- performing a second ECC operation on the data in response to the first ECC operation failing, wherein the second ECC operation uses hard data or soft data to correct errors in the data and wherein performing the second ECC operation includes performing ECC operations on codewords that failed the first ECC operations and include changed bits from a bit flip candidate list based on a log likelihood ratio.
An apparatus, comprising:
- a memory device;
- a controller coupled to the memory device configured to:
- perform a first number of error code correction (ECC) operations on data, wherein the first number of ECC operations use hard data to correct errors in the data;
- and
- perform a second number of ECC operations in response to the first number of ECC operations failing, wherein the second number of ECC operations use soft data to correct errors in the data, wherein the second number of ECC operations include changed bits from a bit flip candidate list based on a log likelihood ratio.
2 more elements
A method, comprising:
- performing a first number of error code correction (ECC) operations on data read from a memory array, wherein the first number of ECC operations use hard data to correct errors in the data;
- and
- performing a second number of ECC operations on the data comprising creating a list of bit flip candidates in response to the first number of ECC operations failing to an error occurring at one or more intersections of column codewords and row codewords, further comprising creating the list of bit flip candidates using bit flip candidates selected based on a log likelihood ratio from bits at the one or more intersections of the row codewords and column codewords where an error remains.
Dependencies are inferred from the claim text.