Semiconductor integrated circuit, receiving apparatus, and memory device

A semiconductor integrated circuit comprising:

• a first circuit configured to output a second signal obtained by changing a frequency characteristic of a first signal, the first signal including a pattern that has a first period and has a second period after the first period, the first period being a period in which the first signal has a first level, the second period being a period in which the first signal has a second level, the second level being different from the first level;
• and
• a second circuit configured to sample an amplitude of the output second signal at a plurality of timings every given cycle in a period corresponding to the second period of the pattern, and to control a parameter relating to the frequency characteristic for the first circuit according to a first magnitude relation and a second magnitude relation, the first magnitude relation being a relation between an absolute value of a first amplitude and a first threshold, the first amplitude being an amplitude sampled at a first timing among the plurality of timings, the second magnitude relation being a relation between an absolute value of a second amplitude and the first threshold, the second amplitude being an amplitude sampled at a second timing, the second timing being a timing after the first timing among the plurality of timings.