System and method of FN-PLL with multi modulus divider

A phase locked loop (PLL) comprising:

• a clock modification circuit having an input coupled to a clock output of the PLL, the clock modification circuit configured to remove a non-integer number of clock cycles from an input clock signal at its input based on a clock modification control signal;
• a multi-modulus divider (MMD) having an input coupled to an output of the clock modification circuit;
• a delta-sigma modulator (DSM) having an output coupled to a modulus control input of the MMD and an input configured to receive a divider input control value;
• an operating point modification circuit coupled to the DSM;
• and
• a controller configured to repeatedly assert the clock modification control signal when a fractional component of the divider input control value is within a first range of values, and to cause the operating point modification circuit adjust an operating point of the DSM to compensate for the removed non-integer number of clock cycles.

A phase locked loop (PLL) comprising:

• a phase comparison circuit configured to receive a reference clock signal at a first input;
• a filter coupled to an output of the phase comparison circuit;
• an oscillator having a frequency control input coupled to an output of the filter;
• a prescaler circuit coupled to an output of the oscillator;
• a clock synchronizer circuit coupled to the prescaler circuit, the clock synchronizer circuit configured to switch between a non-inverted output of the prescaler circuit and an inverted output of the prescaler circuit;
• a multi-modulus divider (MMD) having an input coupled to an output of the clock synchronizer circuit and an output coupled to a second input of the phase comparison circuit;
• a delta-sigma modulator (DSM) having an output coupled to a modulus control input of the MMD and configured to receive a divider input control signal;
• and
• a controller configured to, when the divider input control signal is within a first predetermined range of values, repeatedly cause the clock synchronizer circuit to switch between the non-inverted output of the prescaler circuit and the inverted output of the prescaler circuit, and add a non-integer offset to the divider input control signal received by the MMD.