Vertical thin-film transistors between metal layers

A method for forming a vertical thin film transistor (TFT), the method comprising:

• forming a first short via coupled to a first metal electrode located in a first metal layer, wherein the first metal layer is above a substrate oriented in a horizontal direction;
• forming a channel layer including a channel material, wherein a first portion of the channel layer is coupled to the first short via, the channel layer is oriented in a vertical direction substantially orthogonal to the horizontal direction;
• forming a first dielectric layer including a gate dielectric material within an opening of the channel layer, wherein the first dielectric layer is oriented in the vertical direction, and adjacent to the channel layer;
• forming a gate electrode within an opening of the first dielectric layer, wherein the gate electrode is oriented in the vertical direction, and adjacent to the first dielectric layer;
• forming a second dielectric layer including a second dielectric material within the opening of the first dielectric layer, adjacent to the gate electrode, and coplanar with the first dielectric layer;
• forming a second short via coupled to a second portion of the channel layer and separated from the gate electrode;
• and
• forming a second metal electrode located in a second metal layer, wherein the second metal electrode is coupled to the second short via.

A computing device, comprising:

• a circuit board;
• and
• a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes a transistor and a storage cell, and wherein the transistor includes:
• a gate electrode coupled to a word line of the memory array, wherein a substrate is below the gate electrode in a horizontal direction, and the gate electrode is above the substrate, oriented in a vertical direction substantially orthogonal to the horizontal direction;
• a gate dielectric layer including a gate dielectric material, the gate dielectric layer oriented in the vertical direction, around the gate electrode, and above the substrate;
• a channel layer including a channel material, the channel layer oriented in the vertical direction, around the gate dielectric layer, and above the substrate;
• a first metal electrode located in a first metal layer, and a first short via above the channel layer, wherein the first metal electrode is coupled to the first short via, the first short via is coupled to a first portion of the channel layer and separated from the gate electrode, and the first metal electrode is coupled to a bit line of the memory array;
• and
• a second metal electrode located in a second metal layer, and a second short via below the channel layer, wherein the second metal electrode is coupled to the second short via, the second short via is coupled to a second portion of the channel layer and separated from the gate electrode, and the second metal electrode is coupled to a first electrode of the storage cell;
• and
• the storage cell further includes a second electrode coupled to a source line of the memory array.