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US 11,416,736 B2Granted
Dense digital arithmetic circuitry utilization for fixed-point machine learning
AssigneeIntel Corporation
InventorsKevin Nealis, Randy Huang
Life of this patent
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Abstract
Systems and methods are related to improving throughput of neural networks in integrated circuits by combining values in operands to increase compute density. A system includes an integrated circuit (IC) having multiplier circuitry. The IC receives a first value and a second value in a first operand. The IC performs a multiplication operation, via the multiplier circuitry, on the first operand and a second operand to produce a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value.
Claims20
An integrated circuit device comprising:
- programmable logic circuitry;
- multiplier circuitry;
- and
- first input circuitry to the multiplier circuitry, wherein the first input circuitry is configurable to receive a first operand, wherein a first component of the first operand comprises a first value, a second component of the first operand comprises a second value, and a third component of the first operand comprises a third value;
- and
- second input circuitry to the multiplier circuitry, wherein the second input circuitry is configurable to receive a second operand, wherein a first component of the second operand comprises a fourth value, a second component of the second operand comprises a fifth value, and a third component of the second operand comprises a sixth value, wherein the multiplier circuitry is configurable to multiply components of the first operand and the second operand to produce a plurality of results corresponding to a plurality of distinct multiply operations, wherein the plurality of results comprises:
- a first result of the plurality of results, wherein the first result is a product of a first multiply operation based on the first value and the fourth value;
- a second result of the plurality of results, wherein the second result is a product of a second multiply operation based on the second value and the fifth value;
- and
- a third result of the plurality of results, wherein the third result is a product of a third multiply operation based on the third value and the sixth value.
7 more elements
A method comprising:
- receiving, via a first input circuitry, a first component of a first operand that comprises a first value, a second component of the first operand that comprises a second value, and a third component of the first operand that comprises a third value;
- receiving, via a second input circuitry, a first component of a second operand that comprises a fourth value, a second component of the second operand that comprises a fifth value, and a third component of the second operand comprises a sixth value;
- multiplying the first operand and the second operand to produce a plurality of results corresponding to a plurality of distinct multiply operations, wherein the plurality of results comprises:
- a first result of the plurality of results, wherein the first result is equivalent to a product of a first multiply operation based on the first value and the fourth value;
- a second result of the plurality of results, wherein the second result is a product of a second multiply operation based on the second value and the fifth value;
- and
- a third result of the plurality of results, wherein the third result is a product of a third multiply operation based on the third value and the sixth value.
4 more elements
A system, comprising an integrated circuit device, wherein the integrated circuit device comprises:
- programmable logic circuitry;
- multiplier circuitry;
- first input circuitry to the multiplier circuitry, wherein the first input circuitry is configurable to receive a first operand, wherein a first component of the first operand comprises a first value, a second component of the first operand comprises a second value, and a third component of the first operand comprises a third value;
- and
- second input circuitry to the multiplier circuitry, wherein the second input circuitry is configurable to receive a second operand, wherein a first component of the second operand comprises a fourth value, a second component of the second operand comprises a fifth value, and a third component of the second operand comprises a sixth value, wherein the multiplier circuitry is configurable to multiply the first operand and the second operand to produce a plurality of results corresponding to a plurality of distinct multiply operations, wherein the plurality of results comprises:
- a first result of the plurality of results, wherein the first result is a product of a first multiply operation based on the first value and the fourth value;
- a second result of the plurality of results, wherein the second result is a product of a second multiply operation based on the second value and the fifth value;
- and
- a third result of the plurality of results, wherein the third result is a product of a third multiply operation based on the third value and the sixth value.
6 more elements
Dependencies are inferred from the claim text.