US 11,411,565 B2Granted

Clock and data recovery circuit

AssigneeSTMicroelectronics International N.V.

InventorsRupesh Singh, Ankur Bal

Life of this patent

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Abstract

A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

Claims25

Dependent claims

A circuit, comprising:

a first sampling circuit configured to take a plurality of phase offset first samples of a received serial data stream in response to a first edge of a sampling clock;
a second sampling circuit configured to take a plurality of phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, wherein the second edge is opposite the first edge;
a first comparator circuit configured to determine whether the plurality of phase offset first samples have a same logic state;
a second comparator circuit configured to determine whether the plurality of phase offset second samples have a same logic state;
a first selection circuit configured to select one of the first samples or one of the second samples in response to the determinations made by the first and second comparator circuits;
and
a serial to parallel converter circuit configured to generate an output word including the selected one of the first and second samples.

4 more elements

A method, comprising:

sampling a received serial data stream in response to a first edge of a sampling clock to obtain a plurality of phase offset first samples;
sampling the received serial data stream in response to a second edge of the sampling clock, wherein the second edge is opposite the first edge, to obtain a plurality of phase offset second samples;
determining whether the plurality of phase offset first samples have a same logic state;
determining whether the plurality of phase offset second samples have a same logic state;
first selecting one of the first samples or one of the second samples in response to results of the determining steps;
and
including the selected one of the first and second samples for a serial to parallel conversion to generate an output word.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/131,917Filed 23 Dec 2020 · us provisional application
Priority: 6 Jan 2020
Published: US 2021/0211133 A18 Jul 2021
Granted: 9 Aug 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03L 7/0807
Details of the phase-locked loop: concerning mainly a recovery circuit for the reference signal
H04L 7/0338
Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals: the correction…
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
H03L 7/091
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…