Parallel processor in associative content addressable memory

A parallel processor, comprising:

• a plurality of bit cells, each bit cell comprising:
• an addressable memory bit;
• and
• a first addressable logic operator connected to the addressable memory bit;
• and
• a first arithmetic logic unit (ALU) configured to compute a first function of outputs from the first addressable logic operators of the plurality of bit cells,
• wherein the first ALU is further configured to compute a second function in parallel time with the first function.

A parallel processor, comprising:

• a plurality of bit cells, each bit cell comprising:
• an addressable memory bit;
• and
• a first addressable logic operator connected to the addressable memory bit;
• and
• a first arithmetic logic unit (ALU) configured to compute a first function of outputs from the first addressable logic operators of the plurality of bit cells,
• wherein the first ALU is further configured to compute a second function in serial time with the first function.

A parallel processor, comprising:

• a plurality of bit cells, each bit cell comprising:
• an addressable memory bit;
• and
• a first addressable logic operator connected to the addressable memory bit;
• and
• a first arithmetic logic unit (ALU) configured to compute a first function of outputs from the first addressable logic operators of the plurality of bit cells,
• wherein the first function of the first ALU comprises a programmable threshold function.

A parallel processor, comprising:

• a plurality of bit cells, each bit cell comprising:
• an addressable memory bit;
• and
• a first addressable logic operator connected to the addressable memory bit;
• and
• a first arithmetic logic unit (ALU) configured to compute a first function of outputs from the first addressable logic operators of the plurality of bit cells;
• wherein the plurality of bit cells comprises a first row of bit cells;
• wherein the first ALU is connected to the first row of bit cells;
• and
• wherein the first function of the first ALU comprises a matrix vector product operation.

A parallel processor, comprising:

• a plurality of bit cells, each bit cell comprising:
• an addressable memory bit;
• and
• a first addressable logic operator connected to the addressable memory bit;
• and
• a first arithmetic logic unit (ALU) configured to compute a first function of outputs from the first addressable logic operators of the plurality of bit cells,
• wherein each bit cell further comprises
• a second addressable logic operator coupled to the addressable memory bit and a multiplexer selectively providing a corresponding output from the first addressable logic operator or the second addressable logic operator.

A memory device for performing logical operations, the memory device comprising:

• a plurality of rows of bit cells comprising content-addressable memory;
• and
• a plurality of row arithmetic logic units (ALUs), each row ALU being communicatively coupled to a respective one of the plurality of rows of bit cells;
• wherein each row ALU is configured to perform an operation on outputs from the respective one of the plurality of rows of bit cells;
• wherein each of the plurality of rows of bit cells is subdivided into a plurality of subrows;
• and
• wherein each row ALU adds incoming local population counts of all subrows in the respective row and computes the operation based on a total population count of bit cell results for the respective row.

A memory device for performing logical operations, the memory device comprising:

• a plurality of rows of bit cells comprising content-addressable memory;
• a plurality of row arithmetic logic units (ALUs), each row ALU being communicatively coupled to a respective one of the plurality of rows of bit cells;
• a plurality of memory banks, each comprising a subset of the plurality of rows of bit cells;
• and
• a plurality of bank adders to sum an output from respective ALUs in each of the plurality of memory banks;
• wherein each row ALU is configured to perform an operation on outputs from the respective one of the plurality of rows of bit cells.