Identifying random bits in control data packets

A method, comprising:

• receiving, by input logic, control data packets and an input data clock signal, each control data packet including a set of primitive data bits and a set of random bits;
• identifying, by the input logic, the random bits in the received control data packets to facilitate the creation of modified control data packets;
• generating an internal data clock signal;
• and
• outputting, by the output logic, the modified control data packets to a fluid ejection controller of a fluid ejection device based on the internal data clock signal.

An apparatus, comprising:

• an input shift register to serially receive control data packets and an input data clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the set of random bits for each control data packet has a pseudo-random length;
• modification logic to modify at least one of positions or values of bits in the received control data packets to facilitate the creation of the modified control data packets;
• a clock signal generator to generate an internal data clock signal that is faster than or equal to the input data clock signal;
• and
• an output shift register to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the input data clock signal.