US 11,405,030 B1Granted

Cascode bias for comparator

AssigneeTexas Instruments Incorporated

InventorsManish Mustafi, Amal Kumar Kundu

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Abstract

A comparator having: a first transistor coupled to a first input terminal; a first current source coupled to the first transistor; a second transistor coupled to a second input terminal and coupled to the first current source; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in series with the first transistor; a sixth transistor coupled in series with the second transistor; a seventh transistor coupled to the first input terminal and coupled as a source follower to the fifth transistor; and an eighth transistor coupled to the second input terminal and coupled as a source follower to the sixth transistor. The comparator also including a differential amplifier coupled to the first output terminal and coupled to the second output terminal.

Claims20

Dependent claims

A comparator comprising:

a first transistor having a first control terminal coupled to a first input terminal, a first current handling terminal and a second current handling terminal;
a first current source having a first terminal adapted to be coupled to a supply potential and a second terminal coupled to the first current handling terminal;
a second transistor having a second control terminal coupled to a second input terminal, a third current handling terminal coupled to the first current handling terminal and a fourth current handling terminal;
a third transistor having a third control terminal coupled to the first input terminal, a fifth current handling terminal coupled to the second current handling terminal, and a sixth current handling terminal coupled to a first output terminal;
a fourth transistor having a fourth control terminal coupled to the second input terminal, a seventh current handling terminal coupled to the fourth current handling terminal, and an eighth current handling terminal coupled to a second output terminal;
a fifth transistor having a fifth control terminal, a ninth current handling terminal coupled to the second current handling terminal and a tenth handling terminal coupled to the first output terminal;
a sixth transistor having a sixth control terminal, an eleventh current handling terminal coupled to the fourth current handling terminal and a twelfth current handling terminal coupled to the second output terminal;
a seventh transistor having a seventh control terminal coupled to the first input terminal, a thirteenth current handling terminal adapted to be coupled to the supply potential and a fourteenth current handling terminal coupled to the fifth control terminal;
an eighth transistor having an eighth control terminal coupled to the second input terminal, a fifteenth current handling terminal adapted to be coupled to the supply potential and a sixteenth current handling terminal coupled to the sixth control terminal;
a second current source having a third terminal coupled to the fifth control terminal and a fourth terminal coupled to a reference potential;
a third current source having a fifth terminal coupled to the sixth control terminal and a sixth terminal coupled to the reference potential;
and
a differential amplifier having a non-inverting input terminal coupled to the first output terminal and an inverting input terminal coupled to the second output terminal, the differential amplifier configured to provide a first output signal on a third output terminal when a first voltage on the non-inverting input terminal is greater than a second voltage, on the inverting input terminal;
and configured to provide a second output signal on the third output terminal when the first voltage on the non-inverting input terminal is greater than the second voltage on the inverting input terminal.

11 more elements

An integrated circuit comprising:

a comparator, the comparator including:
a first transistor having a first control terminal coupled to a first input terminal, a first current handling terminal, a second current handling terminal and a first body connection;
a first current source adapted to be coupled between a supply potential and the first current handling terminal;
a second transistor having a second control terminal coupled to a second input terminal, a third current handling terminal coupled to the first current handling terminal, a fourth current handling terminal and a second body connection coupled to the first body connection;
a third transistor having a third control terminal coupled to the first input terminal, a fifth current handling terminal coupled to the second current handling terminal, and a sixth current handling terminal coupled to a first output terminal:
a fourth transistor having a fourth control terminal coupled to the second input terminal, a seventh current handling terminal coupled to the fourth current handling terminal, and an eighth current handling terminal coupled to a second output terminal;
a fifth transistor having a fifth control terminal, a ninth current handling terminal coupled to the second current handling terminal and a tenth handling terminal coupled to the first output terminal;
a sixth transistor having a sixth control terminal, an eleventh current handling terminal coupled to the fourth current handling terminal and a twelfth current handling terminal coupled to the second output, terminal;
a seventh transistor having a seventh control terminal coupled to the first input terminal, a thirteenth current handling terminal adapted to be coupled to the supply potential and a fourteenth current handling terminal coupled to the fifth control terminal;
an eighth transistor having an eighth control terminal coupled to the second input terminal, a fifteenth current handling terminal adapted to be coupled to the supply potential and a sixteenth current handling terminal coupled to the sixth control terminal;
a second current source having a third terminal coupled to the fifth control terminal and a fourth terminal coupled to a reference potential;
a third current source having a fifth terminal coupled to the sixth control terminal and a sixth terminal coupled to the reference potential;
a fourth current source having a seventh terminal coupled to the supply potential and an eighth terminal coupled to the first body connection of the first transistor and the second body connection of the second transistor;
a resistor having a ninth terminal coupled to the eighth terminal and a tenth terminal;
a ninth transistor having a control terminal coupled to the first current handling terminal and the third current handling terminal, a seventeenth current handling terminal coupled to the tenth terminal and an eighteenth current handling terminal coupled to the reference potential;
and
a differential amplifier having a non-inverting input terminal coupled to the first output terminal and an inverting input terminal coupled to the second output terminal, the differential amplifier configured to provide a first output signal on a third output terminal when a first voltage on the non-inverting input terminal is greater than a second, voltage on the inverting input terminal, and configured to provide a second output signal on the third output terminal when the first voltage on the non-inverting input terminal is greater than the second voltage on the inverting input terminal.

14 more elements

An integrated circuit comprising:

a comparator, the comparator including:
a first transistor having a first control terminal coupled to a first input terminal, a first current handling terminal, a second current handling terminal and a first body connection;
a first current source adapted to be coupled between a supply potential and the first current handling terminal;
a second transistor having a second control terminal coupled to a second input terminal, a third current handling terminal coupled to the first current handling terminal, a fourth current, handling terminal and a second body connection coupled to the first body connection;
a third transistor having a third control terminal coupled to the first input terminal, a fifth current handling terminal coupled to the second current handling terminal, and a sixth current handling terminal coupled to a first output terminal;
a fourth transistor having a fourth control terminal coupled to the second input terminal, a seventh current handling terminal coupled to the fourth current handling terminal, and an eighth current handling terminal coupled to a second output terminal;
a fifth transistor having a fifth control terminal, a ninth current handling terminal coupled to the second current handling terminal and a tenth handling terminal coupled to the first output terminal;
a sixth transistor having a sixth control terminal, an eleventh current handling terminal coupled to the fourth current handling terminal and a twelfth current handling terminal coupled to the second output terminal;
a seventh transistor having a seventh control terminal coupled to the first input terminal, a thirteenth current handling terminal adapted to be coupled to the supply potential and a fourteenth current handling terminal coupled to the fifth control terminal;
an eighth transistor having an eighth control terminal coupled to the second input terminal, a fifteenth current handling terminal adapted to be coupled to the supply potential and a sixteenth current handling terminal coupled to the sixth control terminal;
and
a differential amplifier having a non-inverting input terminal coupled to the first output terminal and an inverting input terminal coupled to the second output terminal, wherein the differential amplifier is configured to transition from providing a first output signal to providing a second output signal when a first voltage on the first output terminal is at least a threshold greater than a second voltage on the second output terminal, and is configured to transition from providing the second output signal to providing the first output signal when the second voltage is at least the threshold greater than the first voltage.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/406,583Filed 19 Aug 2021
Granted: 2 Aug 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03K 5/2481
Using field effect transistors: with at least one differential stage
H03F 1/08
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements: modifications of…
H03F 3/26
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements: push-pull amplifiers; Phase-splitters therefor
H03F 3/45089
Long tailed pairs: non-folded cascode stages