Three-dimensional semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsYounghwan Son, Jeehoon Han
Life of this patent
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Abstract
Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.
Claims20
A three-dimensional (3D) semiconductor memory device comprising:
- a substrate;
- an electrode structure on the substrate, the electrode structure comprising gate electrodes stacked in a first direction vertical to a top surface of the substrate, and the gate electrodes including electrode pad regions;
- and
- a dummy vertical structure penetrating one of the electrode pad regions,
- wherein the dummy vertical structure comprises:
- a dummy vertical semiconductor pattern extending substantially in the first direction to penetrate the one of the electrode pad regions and extending into the substrate;
- a dummy data storage pattern between the dummy vertical semiconductor pattern and the substrate;
- and
- a contact pattern extending from a bottom portion of the dummy vertical semiconductor pattern, penetrating a portion of the dummy data storage pattern, and extending into the substrate.
A three-dimensional (3D) semiconductor memory device comprising:
- a substrate including a cell array region and a connection region;
- an electrode structure on the substrate, the electrode structure comprising gate electrodes stacked in a first direction vertical to a top surface of the substrate, and the gate electrodes including electrode pad regions on the connection region;
- a vertical semiconductor pattern penetrating the electrode structure on the cell array region;
- a dummy vertical semiconductor pattern penetrating one of the electrode pad regions on the connection region and extending into the substrate;
- a dummy data storage pattern between the dummy vertical semiconductor pattern and the substrate;
- and
- a contact pattern extending from a bottom portion of the dummy vertical semiconductor pattern into the substrate and penetrating a portion of the dummy data storage pattern.
A three-dimensional (3D) semiconductor memory device comprising:
- a substrate;
- an electrode structure on the substrate, the electrode structure comprising gate electrodes stacked in a first direction vertical to a top surface of the substrate, and the gate electrodes including electrode pad regions;
- a source conductive pattern between the substrate and the electrode structure;
- a dummy vertical semiconductor pattern that penetrates one of the electrode pad regions, penetrates the source conductive pattern under the one of the electrode pad regions, and extends into the substrate;
- a dummy data storage pattern between the dummy vertical semiconductor pattern and the substrate;
- and
- a contact pattern extending from a bottom portion of the dummy vertical semiconductor pattern and penetrating a portion of the dummy data storage pattern to electrically connect to the substrate.
Dependencies are inferred from the claim text.