Memory system and semiconductor storage device configured to discharge word line during abrupt power interrupt

A memory system comprising:

• a semiconductor storage device;
• a power supply circuit configured to generate a first power;
• and
• a memory controller configured to operate based on the first power and to transmit a command to the semiconductor storage device,
• wherein the semiconductor storage device includes:
• a first terminal to which the first power is input;
• a second terminal to which a second power is input, the second power can be used even after a voltage of the first terminal decreases;
• a word line connected to a control gate of a memory cell transistor, to which the command is applied;
• a first circuit configured to apply a voltage according to the command to the word line based on the first power input to the first terminal;
• a second circuit configured to discharge charge of the word line by using the second power input to the second terminal when the voltage of the first terminal decreases;
• a first capacitor configured to store the second power, wherein the first power being input to the first terminal and provided to the first circuit, and the second power is input from the first capacitor to the second terminal;
• and
• a second capacitor, different from the first capacitor,
• the second capacitor configured to store the first power generated by the power supply circuit,
• wherein the power supply circuit is configured to generate the first power based on a third power supplied from an external power supply, and
• when a voltage of the third power decreases, the first power stored in the second capacitor is input to the first terminal.