Efficient polyphase architecture for interpolator and decimator

A system for a polyphase interpolator, comprising:

• a memory;
• and
• a processor configured to:
• add, by an adder, an output of a first subfilter and an output of a second subfilter, wherein the first subfilter has symmetrical coefficients h1+h2 of N samples and the second subfilter has symmetrical coefficients h1−h2 of N samples;
• subtract, by a subtractor, the output of the second subfilter from the output of the first subfilter;
• multiply, by a multiplier, N samples by a constant;
• receive, by a parallel-to-serial (P2S) converter, a number of samples as a parallel input from the adder, the subtractor, and the multiplier;
• and
• generate, by the P2S converter, the number of samples in series,
• wherein the symmetrical coefficients of the subfilters are generated from coefficients in an initial set of coefficients, where the coefficients in the initial set of coefficients exhibit antisymmetric pair properties.

A polyphase interpolator, comprising:

• an adder that adds an output of a first subfilter and an output of a second subfilter, wherein the first subfilter has symmetrical coefficients h1+h2 of N samples and the second subfilter has symmetrical coefficients h1−h2 of N samples;
• a subtractor that subtracts the output of the second subfilter from the output of the first subfilter;
• a multiplier that multiplies N samples by a constant;
• and
• a parallel-to-series (P2S) converter that receives a number of samples as a parallel input from the adder, the subtractor, and the multiplier, and generates the number of samples in series,
• wherein the symmetrical coefficients of the subfilters are generated from coefficients in an initial set of coefficients, where the coefficients in the initial set of coefficients exhibit antisymmetric pair properties.