Memory cell arrangement and methods thereof

A memory cell arrangement comprising:

• a plurality of spontaneous-polarizable memory cells;
• and
• a control circuit configured to cause a writing of one or more first memory cells of the plurality of spontaneous-polarizable memory cells by a writing operation, wherein the writing operation comprises:
• supplying a write signal set to the plurality of spontaneous-polarizable memory cells to provide a write voltage drop at each of the one or more first memory cells to bring each of the one or more first memory cells into a memory state of at least two memory states by switching a respective polarization state of each of the one or more first memory cells, the write signal set causing a disturb voltage drop at one or more second memory cells of the plurality of spontaneous-polarizable memory cells that are not intended to be written, wherein the disturb voltage drop causes a disturb of the one or more second memory cells and maintains a respective polarization state of each of the one or more second memory cells;
• and
• wherein the control circuit is further configured to supply a counter-disturb signal set to the plurality of spontaneous-polarizable memory cells, wherein the counter-disturb signal set provides a counter-disturb voltage drop at the one or more second memory cells to at least partially compensate the disturb caused by the disturb voltage drop.