Apparatuses and methods for pre-emphasis control

An apparatus comprising:

• a pull-up circuit configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal;
• a pull-down circuit configured to receive a pull-down activation signal and drive the data terminal to a pull-down voltage responsive to an active pull-down data activation signal;
• and
• a pre-emphasis circuit configured to receive at least one of the pull-up and pull-down data activation signals and configured to further receive control signals to set a mode of operation and provide pre-emphasis responsive to the at least one of the active pull-up and pull-down data activation signals, the pre-emphasis circuit including a pre-emphasis timing control circuit configured to provide a timing control signal based on the at least one of the pull-up and pull-down data activation signals and further including a logic circuit configured to provide a pre-emphasis control signal based on the at least one of the pull-up and pull-down data activation signals and the timing control signal to control providing pre-emphasis having a timing based on the mode of operation set by the control signals, wherein the pre-emphasis timing control circuit comprises:
• a first NAND gate circuit configured to receive the data activation signal and a pre-emphasis enable signal and to provide a first output signal;
• a second NAND gate circuit configured to receive the first output signal and a first control signal and to provide a second output signal;
• a third NAND gate circuit configured to receive the second output signal and the data activation signal and to provide a third output signal;
• a fourth NAND gate circuit configured to receive the third output signal and the pre-emphasis enable signal and to provide a fourth output signal;
• and
• a fifth NAND gate circuit configured to receive the fourth output signal and a second control signal and provide the timing control signal.

An apparatus comprising:

• a pull-up circuit configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal;
• a pull-down circuit configured to receive a pull-down activation signal and drive the data terminal to a pull-down voltage responsive to an active pull-down data activation signal;
• and
• a pre-emphasis circuit configured to receive at least one of the pull-up and pull-down data activation signals and configured to further receive control signals to set a mode of operation and provide pre-emphasis responsive to the at least one of the active pull-up and pull-down data activation signals, the pre-emphasis circuit including a pre-emphasis timing control circuit configured to provide a timing control signal based on the at least one of the pull-up and pull-down data activation signals and further including a logic circuit configured to provide a pre-emphasis control signal based on the at least one of the pull-up and pull-down data activation signals and the timing control signal to control providing pre-emphasis having a timing based on the mode of operation set by the control signals, wherein the pre-emphasis timing control circuit comprises:
• a first NAND gate circuit configured to receive the data activation signal and a pre-emphasis enable signal and to provide a first output signal;
• a second NAND gate circuit configured to receive the first output signal and to further receive a first control signal or a logic high voltage, and further configured to provide a second output signal;
• a third NAND gate circuit configured to receive the data activation signal and the second output signal and to provide a third output signal;
• a fourth NAND gate circuit configured to receive the third output signal and to further receive the first control signal or a logic high voltage, and further configured to provide a fourth output signal;
• a fifth NAND gate circuit configured to receive the fourth output signal and the data activation signal and to provide a fifth output signal;
• a sixth NAND gate circuit configured to receive the fifth output signal and the pre-emphasis enable signal and to provide a sixth output signal;
• and
• a seventh NAND gate circuit configured to receive the sixth output signal and a second control signal and provide the timing control signal.

An apparatus comprising:

• a pull-up circuit configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal;
• a pull-down circuit configured to receive a pull-down activation signal and drive the data terminal to a pull-down voltage responsive to an active pull-down data activation signal;
• and
• a pre-emphasis circuit configured to receive at least one of the pull-up and pull-down data activation signals and configured to further receive control signals to set a mode of operation and provide pre-emphasis responsive to the at least one of the active pull-up and pull-down data activation signals, the pre-emphasis circuit including a pre-emphasis timing control circuit configured to provide a timing control signal based on the at least one of the pull-up and pull-down data activation signals and further including a logic circuit configured to provide a pre-emphasis control signal based on the at least one of the pull-up and pull-down data activation signals and the timing control signal to control providing pre-emphasis having a timing based on the mode of operation set by the control signals, wherein the pre-emphasis timing control circuit comprises:
• control logic configured to receive first and second control signals and provide a third control signal based on states of the first and second control signals;
• a first NAND gate circuit configured to receive the data activation signal and a pre-emphasis enable signal and to provide a first output signal;
• a second NAND gate circuit configured to receive the first output signal and to further receive the third control signal, and further configured to provide a second output signal;
• a third NAND gate circuit configured to receive the data activation signal and the second output signal and to provide a third output signal;
• a fourth NAND gate circuit configured to receive the third output signal and to further receive the third control signal, and further configured to provide a fourth output signal;
• a fifth NAND gate circuit configured to receive the fourth output signal and the data activation signal and to provide a fifth output signal;
• a sixth NAND gate circuit configured to receive the fifth output signal and the pre-emphasis enable signal and to provide a sixth output signal;
• and
• a seventh NAND gate circuit configured to receive the sixth output signal and a second control signal and provide the timing control signal,
• wherein the control logic is configured to provide an active third control signal to the second NAND gate circuit responsive to a first combination of states for the first and second control signals and provide the active third control signal to the fourth NAND gate circuit responsive to a second combination of states for the first and second control signals.

An apparatus, comprising:

• a pull-up circuit configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal;
• a pull-down circuit configured to receive a pull-down activation signal and drive the data terminal to a pull-down voltage responsive to an active pull-down data activation signal;
• and
• a pre-emphasis circuit configured to receive at least one of the pull-up and pull-down data activation signals and to further receive control signals to set a mode of operation, and provide pre-emphasis responsive to the active at least one of the pull-up and pull-down data activation signals, the pre-emphasis circuit including a pre-emphasis timing control circuit configured to provide a timing control signal and further including a logic circuit configured to provide a pre-emphasis control signal based on the at least one of the pull-up and pull-down data activation signals and the timing control signal to control providing pre-emphasis with a first timing responsive to a first mode of operation, with a second timing responsive to a second mode of operation, and a third timing responsive to a third mode of operation, wherein
• the pre-emphasis timing control circuit is configured to provide in the first mode of operation the timing control signal to control providing pre-emphasis for greater than one unit interval of data when the at least one of the pull-up and pull-down data activation signals remains active for greater than one unit interval, and further provide in the third mode of operation the timing control signal to control providing pre-emphasis continuously when the data activation signal is active.

A method, comprising:

• providing pre-emphasis responsive to an active data activation signal;
• in a first mode of operation:
• responsive to the data activation signal remaining active for more than one unit interval, continuing to provide pre-emphasis for more than one unit interval and less than two unit intervals, and
• responsive to an inactive data activation signal, ceasing pre-emphasis;
• and
• in a second mode of operation:
• ceasing pre-emphasis within one unit interval.