Data sampling circuit and data sampling device

A data sampling circuit, comprising:

• a first sampling circuit connected to a data signal terminal, a reference signal terminal, a first node, and a second node, wherein the first sampling circuit is configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node;
• a second sampling circuit connected to the first node, the second node, a third node, and a fourth node, wherein the second sampling circuit is configured to respond to a signal from the first node and a signal from the second node and to act on the third node and the fourth node;
• a latch module connected to the third node, the fourth node, a first output terminal, and a second output terminal, wherein the latch module is configured to input a high level signal to the first output terminal and input a low level signal to the second output terminal, or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node;
• and
• a decision feedback equalization module connected in parallel to the second sampling circuit and configured to reduce intersymbol interference;
• wherein the first sampling circuit is further connected to a first clock signal terminal and is configured to start a sampling action in response to a signal from the first clock signal terminal;
• wherein the data sampling circuit further comprises a resetting circuit connected to:
• the first clock signal terminal, a second clock signal terminal, the first node, the second node, the third node, the fourth node, the first output terminal, and the second output terminal;
• wherein the resetting circuit is configured to reset the first node and the second node in response to the signal from the first clock signal terminal, and to reset the third node, the fourth node, the first output terminal and the second output terminal in response to a signal from the second clock signal terminal.