Hierarchical error correction code
AssigneeSamsung Electronics Co., Ltd.
InventorsAmit Berman, Ariel Doubchak
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AssigneeSamsung Electronics Co., Ltd.
InventorsAmit Berman, Ariel Doubchak
Estimating the term…
Embodiments of the present disclosure provide a controller hierarchical decoding architecture. For instance, multiple decoder hierarchies are implemented along with use of hierarchies of codes with locality (e.g., larger code length of a hierarchy is composed of local codes from a lower hierarchy). The hierarchical Error Correction Code (ECC) decoding includes multiple hierarchies such as a first hierarchy, a second hierarchy, and additional hierarchies as needed. A first hierarchy includes low-complexity ECC engines, each connected to a NAND channel for computing local codes of low code lengths. A second hierarchy includes higher complexity ECC engines that shares several NAND channels for correcting corrupt data using relatively larger code length (e.g., and the higher complexity ECC engines of the second hierarchy performs decoding operations using more complex decoding algorithms). The larger code length is composed of local codes from a previous hierarchy.
A method for flash memory error code correction, comprising:
A method for flash memory error code correction, comprising:
An apparatus for flash memory error code correction, comprising:
Dependencies are inferred from the claim text.