System AMD method for a self-calibrating pipelined dynamic preamplifier for high speed comparators in a time-interpolating flash ADC
AssigneeRobert Bosch GmbH
InventorsSangwoo Lee, Sayyed Mahdi Kashmiri, Kenneth Wojciechowski
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Abstract
A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.
Claims20
A system including a circuit in an amplifier, comprising:
- a first preamplifier;
- a sampling switch;
- a regenerative latch;
- and
- a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with a dynamic comparator and configured to amplify a signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.
A pipelined dynamic preamplifier system, comprising:
- a first dynamic preamplifier;
- a second dynamic preamplifier, wherein the first and second dynamic preamplifier are arranged in a pipelined sequence;
- one or more sampling switches;
- and
- a regenerative latch, wherein the regenerative latch is configured to amplify signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.
A method for outputting a digital signal via a pipelined dynamic preamplifier system, comprising:
- arranging in a cascading arrangement a first dynamic preamplifier and a second dynamic preamplifier;
- and
- quantizing the digital signal during a final phase of a sample-and-hold sequence, wherein the quantizing utilizes a regenerative latch.
Dependencies are inferred from the claim text.