SAR analog-to-digital converter calibration
AssigneeMicrosoft Technology Licensing, LLC
InventorsKenneth Colin Dyer, John Paul Rankin
Life of this patent
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Abstract
Embodiments of the present disclosure include techniques for calibrating analog-to-digital converters (ADCs), such as successive approximation register SAR ADCs. In one embodiment, a pattern is applied to the input of an ADC to produce digital output codes. Counts of the digital output codes are used detect errors and adjust a clock delay of a comparator in the ADC. In other embodiments, an ADC calibration circuit is coupled to a calibration algorithm executing on a remote server to calibrate one or more ADCs.
Claims19
A circuit comprising:
- a successive approximation register analog-to-digital converter configured to receive an analog input signal and to generate a plurality of digital output codes corresponding to a plurality of analog input signal values of the analog input signal, the analog-to-digital converter including at least one comparator used to generate the digital output codes, wherein the at least one comparator is coupled to a comparator clock signal;
- and
- a calibration circuit coupled to the analog-to-digital converter, the calibration circuit providing an input signal pattern to the analog-to-digital converter to generate a plurality of counts of the digital output codes across a range of analog input signal values, wherein each of the plurality of counts indicates a number of times a particular digital output code corresponding to a particular analog input signal value was generated,
- wherein errors in the plurality of counts are detected and used to adjust at least one delay of the comparator clock signal to reduce the errors in the plurality of counts.
A method of calibrating a successive approximation register analog-to-digital converter comprising:
- providing an analog input signal pattern to an input of the successive approximation register analog-to-digital converter;
- generating, by the successive approximation register analog-to-digital converter, a plurality of digital output codes representing the analog input signal pattern;
- clocking at least one comparator in the successive approximation register analog-to-digital converter as part of generating the plurality of digital output codes;
- generating a histogram of the digital output codes;
- detecting errors in the digital output codes from the histogram;
- and
- adjusting at least one delay of the clocking of the at least one comparator in response to the detected errors in the histogram.
Dependencies are inferred from the claim text.