Phase-locked loop capable of compensating power noise

A phase-locked loop, comprising:

• a phase frequency detector configured to compare a reference clock signal and a feedback clock signal and to output a detection signal;
• a loop filter configured to filter the detection signal and output a bias control signal;
• a bias circuit configured to control a first bias current between a first power source and a first node according to the bias control signal;
• an oscillation circuit coupled between the first node and a second power source and configured to generate an oscillation signal according to a current from the first node;
• a divider configured to divide the oscillation signal and to output the feedback clock signal;
• a duplicate bias circuit configured to control a second bias current between the first power source and a second node according to the bias control signal;
• an equivalent impedance circuit coupled between the second node and the second power source;
• a comparator circuit configured to compare respective voltages of the first node and the second node;
• a first variable current circuit configured to control a current between the first node and the second power source according to an output of the comparator circuit;
• and
• a second variable current circuit configured to control a current between the second node and the second power source according to the output of the comparator circuit.