Methods and apparatus to implement pulse swallowing circuitry in a phase frequency detector

A phase frequency detector (PFD) comprising:

• a first flip flop having a first output and a first reset input;
• a second flip flop having a first data input, a second output, and a second reset input the second reset input coupled to the first reset input,
• a logic gate having a first logic gate input, a second logic gate input, and first logic gate output, the first logic gate input coupled to the first output and the second logic gate input coupled to the second output,
• a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic gate output and the delay cell output coupled to the first reset input and the second reset input;
• and
• pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input,
• wherein the first flip flop further includes a first clock input, the second flip flop further includes a second clock input, and the pulse swallowing circuitry further comprises:
• a third flip flop having a third clock input, the third clock input and the second clock input configured to receive a modulated clock signal and the first clock input configured to receive a reference clock input, the modulated clock signal having a first frequency that is N times that of a second frequency corresponding to reference clock signal.

A system comprising:

• a phase frequency detector having a first input, a second input, a third input, a first output, and a second output, the second input configured to receive a reference clock signal, and the third input configured to receive a control signal indicative of a ratio between the reference clock signal and the fifth output of the voltage controlled oscillator;
• a charge pump having a third output, the charge pump coupled to the first and second outputs;
• a loop filter having a fourth output, the loop filter coupled to the third output;
• and
• a voltage controlled oscillator coupled to the fourth output and having a fifth output directly coupled to the first input of the phase frequency detector.

A method comprising:

• latching a low voltage at a first flip flop output responsive to a first rising edge on a first clock signal;
• latching a high voltage at a second flip flop output responsive to the first rising edge on the first clock signal;
• inputting a high voltage at a first flip flop input responsive to latching the high voltage at the second flip flop output;
• and
• latching the high voltage on the first flip flop input at the first flip flop output responsive to a second rising edge on the first clock signal, the second rising edge occurring at a time after the first rising edge.