Circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops

A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops, comprising a plurality of phase-locked loops, a data selector and a signal synthesizer, wherein:

• each of input terminals of the plurality of phase-locked loops receives a reference clock signal, output terminals of the plurality of phase-locked loops are connected to input terminals of the data selector respectively, and a first output terminal and a second output terminal of the data selector are connected to two input terminals of the signal synthesizer respectively;
• each of the phase-locked loops is configured to generate a corresponding clock signal based on the reference clock signal, wherein the generated clock signal serves as an output signal of the phase-locked loop;
• the data selector is configured to make a selection on the output signals of the phase-locked loops, wherein the selected signals serve as output signals of the data selector;
• in a case that a clock signal with low jitter is required to be generated, output signals of a first phase-locked loop and a second phase-locked loop are adjusted to be the same in frequency and phase, output signals of other phase-locked loops are adjusted to be different from each other in frequency, the data selector selects output signals to be outputted based on a requirement for the clock signal with low jitter, and the signal synthesizer is enabled to superimpose and then average a first output signal and a second output signal of the data selector, to obtain a clock signal with jitter eliminated;
• and
• in a case that a plurality of clock signals with different frequencies are required to be generated, output signals of the plurality of phase-locked loops are adjusted to be different from each other in frequency, and the plurality of clock signals with different frequencies are obtained through the data selector without enabling the signal synthesizer.