Output driving circuit
AssigneeSK hynix Inc.
InventorSeung Ho Lee
Life of this patent
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Abstract
A semiconductor memory device has an output driving circuit. The output driving circuit includes a pull-down driver and a gate control logic. The pull-down driver includes first and second transistors. The first and second transistors are coupled between a pad and a ground node. The gate control logic includes third and fourth transistors. The third and fourth transistors are coupled between a pad and a first supply voltage node. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage. The first transistor is controlled by the feedback voltage. The second and third transistors are controlled by the first supply voltage. The fourth transistor is controlled by the voltage of the pad.
Claims10
A semiconductor memory device having an output driving circuit, the output driving circuit comprising:
- a pull-down driver including a first transistor and a second transistor, the first and second transistors being coupled between a pad and a ground node, wherein a source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal;
- and
- a gate control logic including a third transistor and a fourth transistor, the third and fourth transistors being coupled between a pad and a first supply voltage node, the gate control logic being configured to receive a voltage of the pad and output a feedback voltage,
- wherein the first transistor is controlled by the feedback voltage, the second and the third transistors are controlled by the first supply voltage, and the fourth transistor is controlled by the voltage of pad.
A output driving circuit comprising:
- a gate control logic configured to receive a pad voltage and a first power supply voltage and generate a feedback voltage;
- and
- a pull-down driver including a first NMOS transistor receiving the feedback voltage, a second NMOS transistor receiving the first power supply voltage and a third NMOS transistor receiving a control signal voltage, the first to third NMOS transistors being electrically coupled between a pad and a ground node, in series,
- wherein the gate control logic includes a first PMOS transistor, a second PMOS transistor and a third PMOS transistor which are sequentially coupled in series, between the pad voltage and the first power supply voltage, and
- wherein the feedback voltage is a voltage applied to bulk regions of the first to third PMOS transistors.
Dependencies are inferred from the claim text.