Pulse signal sending circuit
AssigneeMitsumi Electric Co., Ltd.
InventorKeizo Kumagai
Life of this patent
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Abstract
A pulse signal sending circuit that outputs pulse signals from an output terminal includes: an output transistor; an inverter circuit; and a delay circuit. The output transistor includes a drain terminal connected to the output terminal. The inverter circuit is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor. The delay circuit receives a pulse signal as an input and delays rising or falling of the input pulse signal. The pulse signal delayed by the delay circuit is input to the inverter circuit.
Claims13
A pulse signal sending circuit that outputs an output pulse signal at an output terminal, the circuit comprising:
- an output transistor that includes a drain terminal connected to the output terminal;
- an inverter circuit that is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor;
- and
- a delay circuit that receives an input pulse signal as an input and delays only rising or only falling of the input pulse signal, wherein:
- the input pulse signal delayed by the delay circuit is input to the inverter circuit, and
- a duty cycle of the output pulse signal at the output terminal is controlled to be 50% when a duty cycle of the input pulse signal is 50%.
A pulse signal sending circuit that outputs an output pulse signal at an output terminal, the circuit comprising:
- an output transistor that includes a drain terminal connected to the output terminal;
- an inverter circuit that is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor;
- and
- a delay circuit that receives an input pulse signal as an input and delays only rising or only falling of the input pulse signal,
- wherein:
- the input pulse signal delayed by the delay circuit is input to the inverter circuit,
- the pulse signal sending circuit performs control such that a rising time of the output pulse signal is equal to a falling time thereof, where the rising time is time required for the output pulse signal at the output terminal to rise, and the falling time is time required for the output pulse signal at the output terminal to fall,
- the inverter circuit is a CMOS inverter circuit that includes a P-channel MOS transistor and an N-channel MOS transistor that are connected in series,
- the P-channel MOS transistor is connected in series to a first constant-current source between a first power-supply voltage terminal and an output node, and
- the N-channel MOS transistor is connected in series to a second constant-current source between the output node and a second power-supply voltage terminal.
A pulse signal sending circuit that outputs an output pulse signal at an output terminal, the circuit comprising:
- an output transistor that includes a drain terminal connected to the output terminal;
- an inverter circuit that is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor;
- and
- a delay circuit that receives an input pulse signal as an input and delays only rising or only falling of the input pulse signal, wherein
- the input pulse signal delayed by the delay circuit is input to the inverter circuit, and
- a duty cycle of the output pulse signal at the output terminal is controlled to be equal to a duty cycle of the input pulse signal.
Dependencies are inferred from the claim text.