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US 11,387,817 B2Granted
Latch circuit, flip-flop circuit including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsByoung Gon Kang, Woo Kyu Kim, Tae Jun Yoo, Dal Hee Lee
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Abstract
A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.
Claims16
A master latch circuit comprising:
- a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series between a power supply terminal and a power ground terminal;
- a first node connected to a drain terminal of the first p-type transistor and a drain terminal of the first n-type transistor;
- and
- a NAND circuit configured to receive a signal of the first node and a clock signal, perform a NAND operation, and output a result of the NAND operation to a second node,
- wherein the NAND circuit includes a second p-type transistor connected in parallel with a third p-type transistor between the power supply terminal and the second node, and a third n-type transistor connected in series with a fourth n-type transistor between the second node and the power ground terminal,
- wherein a gate of the second p-type transistor and a gate of the fourth n-type transistor are connected to the first node,
- wherein a gate of the first n-type transistor, a gate of the third p-type transistor, and a gate of the third n-type transistor are configured to receive the clock signal, and
- wherein a gate of the first p-type transistor is connected to the second node.
5 more elements
A flip-flop circuit comprising:
- a scan multiplexer (MUX) circuit having a MUX output terminal connected to a first node;
- a first latch circuit connected between the first node and a second node;
- a second latch circuit connected between the second node and a third node;
- and
- an output driving circuit configured to drive and output a signal of the third node,
- wherein the first latch circuit includes a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series between a power supply terminal and a power ground terminal, and a NAND circuit configured to receive a signal of the first node and a clock signal, and perform a NAND operation and output a result of the NAND operation to the second node,
- wherein the NAND circuit includes a second p-type transistor connected in parallel with a third p-type transistor between the power supply terminal and the second node, and a third n-type transistor connected in series with a fourth n-type transistor between the second node and the power ground terminal,
- wherein a drain terminal of the first p-type transistor and a drain terminal of the first n-type transistor are connected to the first node,
- wherein a gate of the second p-type transistor and a gate of the fourth n-type transistor are connected to the first node,
- wherein a gate of the first n-type transistor, a gate of the third p-type transistor, and a gate of the third n-type transistor are configured to receive the clock signal,
- wherein the first n-type transistor and the second n-type transistor are not simultaneously turned on, and
- wherein a gate of the first p-type transistor is connected to the second node.
9 more elements
Dependencies are inferred from the claim text.