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US 11,387,815 B2Granted
Apparatus and method for improving lock time
AssigneeIntel Corporation
InventorsWilliam Li, Mohsen Nasroullahi, Khoa Nguyen
Life of this patent
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Abstract
An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency monitor coupled to the ring oscillator to monitor frequency at an output of at least two delay stages of the ring oscillator.
Claims16
A frequency or phase locked loop comprising:
- a phase detector or a phase frequency detector to receive a reference clock and a feedback clock;
- a divider coupled to the phase detector or the phase frequency detector, wherein the divider is to generate the feedback clock;
- an oscillator coupled to the divider, wherein the oscillator comprises at least two delay stages coupled together in a ring formation, wherein each delay stage has an adjustable propagation delay;
- and
- a frequency monitor coupled to the at least two delay stages, wherein the frequency monitor is to determine a frequency of a signal at an input and/or an output of the at least two delay stages, wherein the frequency monitor comprises:
- a first counter coupled to the output of a first delay stage of the at least two delay stages;
- and
- a second counter coupled to the output of a second delay stage of the at least two delay stages.
5 more elements
A frequency or phase locked loop comprising:
- a time-to-digital converter to receive a reference clock and a feedback clock;
- a divider coupled to the time-to-digital converter, wherein the divider is to generate the feedback clock;
- an oscillator coupled to the divider;
- a circuitry coupled to the oscillator, wherein the circuitry is to tap intermediate nodes of the oscillator to determine frequency of signals at the intermediate nodes;
- and
- logic to adjust a frequency of the oscillator according to a comparison of an average of the frequency of signals at the intermediate nodes and a target frequency of the oscillator.
3 more elements
A frequency or phase locked loop comprising:
- a phase detector or a phase frequency detector to receive a reference clock and a feedback clock;
- a divider coupled to the phase detector or the phase frequency detector, wherein the divider is to generate the feedback clock;
- an oscillator coupled to the divider, wherein the oscillator comprises at least two delay stages coupled together in a ring formation, wherein each delay stage has an adjustable propagation delay;
- a frequency monitor coupled to the at least two delay stages, wherein the frequency monitor is to determine a frequency of a signal at an input and/or an output of the at least two delay stages;
- and
- a sigma-delta modulator coupled to the divider.
3 more elements
Dependencies are inferred from the claim text.