Frequency multiplier and delay-reused duty cycle calibration method thereof

A frequency multiplier, comprising:

• a first calibration circuit, comprising:
• a first delay cell, configured to provide a first delay;
• wherein in a calibration mode of the frequency multiplier, an output terminal of the first delay cell is coupled to an input terminal of the first delay cell, the first delay cell is repeatedly used M times for delaying an input calibration signal or a derivative thereof by M times the first delay, to generate a first delayed signal, and M is a predetermined positive integer;
• a second calibration circuit, configured to generate the input calibration signal according to an input clock signal;
• a controller, coupled to the first calibration circuit and the second calibration circuit, wherein the controller controls the first delay according to the first delayed signal, to find a target delay which makes M times the target delay be equal to one cycle period of an input clock signal;
• after the target delay is found, the first delay cell is repeatedly used M/2 times for delaying the input calibration signal or the derivative thereof by M/2 times the target delay, to generate a second delayed signal;
• and the controller controls the second calibration circuit according to the second delayed signal to make the input calibration signal have a target duty cycle;
• and
• a phase detector, coupled to the controller, configured to detect a phase difference between a delayed edge of the first delayed signal and a target edge of the input calibration signal;
• wherein the controller controls the first delay to make the delayed edge of the first delayed signal be aligned with the target edge of the input calibration signal.