Power amplifier circuit

A power amplifier circuit comprising:

• a lower-stage transistor having a first terminal, a second terminal, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, the second terminal is connected to ground, and a first signal is supplied to the third terminal;
• a first capacitor;
• an upper-stage transistor having a first terminal, a second terminal, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, a second signal obtained by amplifying the first signal is output from the first terminal, the second terminal is connected to the first terminal of the lower-stage transistor via the first capacitor, and the third terminal is connected to ground via a ground path;
• an inductor that connects the second terminal of the upper-stage transistor to ground;
• and
• an adjustment circuit configured to adjust an impedance seen from the third terminal of the upper-stage transistor, wherein:
• the adjustment circuit comprises the ground path,
• the ground path comprises a second capacitor and at least one resistance element, the second capacitor and the at least one resistance element being connected in series between the third terminal of the upper-stage transistor and ground,
• a first bias current or a first bias voltage is supplied from a first bias circuit via a bias supply path to a supply node,
• the adjustment circuit further comprises a first resistance element connected in the bias supply path between the first bias circuit and the supply node, and
• the at least one resistance element comprises:
• a second resistance element connected between the third terminal of the upper-stage transistor and the supply node, and
• a third resistance element connected between the supply node and ground.

A power amplifier circuit comprising:

• a lower-stage transistor having a first terminal, a second terminal, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, the second terminal is connected to ground, and a first signal is supplied to the third terminal;
• a first capacitor;
• an upper-stage transistor having a first terminal, a second terminal, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, a second signal obtained by amplifying the first signal is output from the first terminal, the second terminal is connected to the first terminal of the lower-stage transistor via the first capacitor, and a bias current or a bias voltage is supplied to the third terminal from a bias circuit via a bias supply path;
• an inductor that connects the second terminal of the upper-stage transistor to ground;
• and
• an adjustment circuit configured to adjust an impedance seen from the third terminal of the upper-stage transistor, wherein:
• the adjustment circuit comprises the bias supply path,
• the bias supply path comprises a third capacitor and a first resistance element, a first end of the third capacitor and a first end of the first resistance element each being connected to an output of the bias circuit, and a second end of the third capacitor and a second end of the first resistance element each being connected to the third terminal of the upper-stage transistor, and
• the third capacitor and the first resistance element are connected in parallel with each other.