Half-bridge circuit with slew rate control

A circuit, comprising:

• a first terminal, a second terminal, and a third terminal, wherein a voltage at said third terminal represents a reference voltage;
• a half-bridge comprising a first n-channel FET and a second n-channel FET connected in series between said first terminal and said second terminal, wherein a first intermediate node between said first n-channel FET and said second n-channel FET represents a switching node;
• a first driver circuit configured to drive a gate terminal of said first n-channel FET as a function of a first drive signal;
• a second driver circuit configured to drive a gate terminal of said second n-channel FET as a function of a second drive signal;
• a voltage regulator configured to generate a first supply voltage at an output terminal as a function of a voltage between said first terminal and said second terminal, wherein said first supply voltage is used to supply said second driver circuit;
• wherein said first driver circuit is a driver circuit without slew-rate control configured to set an output node of said first driver circuit to said reference voltage or to a second supply voltage as a function of said first drive signal;
• a slew-rate circuit, comprising:
• a first resistor and a capacitor connected in series between said output node of said first driver circuit and a second intermediate node;
• a first electronic switch having a first conduction path connected between said second intermediate node and said first terminal;
• a second electronic switch having a second conduction path connected between said second intermediate node and said gate terminal of said first n-channel FET;
• and
• a second resistor and a third conduction path of a third electronic switch connected in series between said gate terminal of said first n-channel FET and said switching node;
• and
• a control circuit configured to:
• for a first time interval, set said first drive signal and said second drive signal to close said first n-channel FET and to open said second n-channel FET, respectively, and set a first control signal, a second control signal and a third control signal to simultaneously open said first electronic switch, open said third electronic switch and close said second electronic switch, respectively;
• and
• for a second time interval, set said first drive signal and said second drive signal to open said first n-channel FET and close said second n-channel FET, respectively, and set said first control signal, said second control signal and said third control signal to simultaneously close said first electronic switch, close said third electronic switch and open said second electronic switch, respectively.